Patents by Inventor Mohit Saxena

Mohit Saxena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10127243
    Abstract: The embodiments relate to performing a write operation in a filesystem. Replica files embedded with respective sets of data are stored are on persistent storage local to replica nodes of the filesystem. The storage includes atomically updating the replica files to the replica nodes. Each set of data has information for self-characterizing each replica file. A map stored at persistent storage local to a remote node is updated. The map maintains information for identifying each replica file stored at each replica node.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventor: Mohit Saxena
  • Patent number: 10114733
    Abstract: A benchmark test system captures and records root, or input, behavior from a user input device as one or more time-displaced samples of input. The system also separately captures and records the canvas, or visual, behavior of a user interface in response to the captured input as a series of time-displaced image frames. The image frames are analyzed for visual prompts occurring responsive to the input, and parameters of the image frames are determined. A parametric difference between corresponding ones of the root events and canvas responses is thereby computed, in order to determine a degree of visual responsiveness for the user interface software respective to the root input.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 30, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Varghese, Mohit Saxena, Anshul Sharma, Arnold Jean-Marie Gustave Ginetti
  • Publication number: 20180307719
    Abstract: In one embodiment, a computer-implemented method for object-granular policy assignment in an object storage environment includes: automatically assigning a plurality of objects stored within the object storage environment to one or more policies; and locating one or more of the objects among a plurality of policy rings within the object storage environment based on semantics of the one or more policies. A virtual namespace maps each object to at least one of the policy rings based on the one or more policies assigned to the object; and the virtual namespace is scalable with a number of the plurality of objects stored within the object storage environment. Corresponding systems and computer program products are also disclosed.
    Type: Application
    Filed: June 27, 2018
    Publication date: October 25, 2018
    Inventors: Nagapramod S. Mandagere, Mohit Saxena
  • Patent number: 10095595
    Abstract: In one embodiment, a system includes a cache storage device, a back-end storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive indication of failure of a primary cache server at a secondary cache server, the primary and secondary cache servers being configured to manage read requests and write requests for the back-end storage device. The logic is also configured to set the secondary cache server to a by-pass mode for read requests directed to any portions of the back-end storage device managed by the primary cache server prior to the failure. Moreover, the logic is configured to read an index of cache block descriptors (CBDs) managed by the primary cache server prior to the failure into a memory of the secondary cache server.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20180267710
    Abstract: In one embodiment, a method includes determining a data record partition size based on resources used for transferring data from a higher storage tier to one or more lower storage tiers. The method also includes determining which data records stored to the higher storage tier are suitable for export to the one or more lower storage tiers, determining a distribution mapping of the first memory, the distribution mapping indicating a relative distribution of storage locations for all of the data records that are stored to the higher storage tier, identifying all sets of contiguously stored data records on the higher storage tier that are suitable for export and greater in size than the data record partition size, logically sorting, in a descending order of size, the sets of contiguously stored data records, and sending a list of logically sorted sets of contiguously stored data records to an exporter.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Umesh Deshpande, Paul H. Muench, Mohit Saxena
  • Publication number: 20180232153
    Abstract: In various embodiments, computer-implemented techniques for improving function of in-memory processing systems via adaptively caching datasets include: identifying data stored in a distributed filesystem, the data including data to be processed by an in-memory processing application and data not to be processed by the in-memory processing application; identifying one or more partitions of the data corresponding to the data to be processed; and selectively transferring the one or more partitions from the distributed filesystem to a memory of the in-memory processing application. Corresponding systems and computer-program products are also disclosed.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Lawrence Y. Chiu, Mohit Saxena, Erci Xu
  • Patent number: 10014881
    Abstract: Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
  • Patent number: 10013214
    Abstract: In various embodiments, techniques for improving function of in-memory processing systems include identifying data stored in a distributed filesystem, including data to be processed by an in-memory processing application and data not to be processed by the in-memory processing application; identifying one or more partitions of the data corresponding to the data to be processed; and selectively transferring the one or more partitions from the distributed filesystem to a memory of the in-memory processing application. Techniques may also include determining an average remote execution time of the in-memory processing system; tracking a waiting time of a job pending processing on a local node of the in-memory processing system; comparing the tracked waiting time of the job pending processing; and demoting a locality of the job if waiting time of the job exceeds the average remote execution time of the in-memory processing system. Corresponding systems and computer-program products are also disclosed.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Y. Chiu, Mohit Saxena, Erci Xu
  • Publication number: 20180165195
    Abstract: In one embodiment, a computer-implemented method includes selecting a cache block descriptor (CBD) from amongst a plurality of CBDs stored to a cache storage device to defragment based on a determination of utilization of a particular fine block descriptor (FBD) having a first size that is allocated to the selected CBD. The cache storage device includes a free pool of FBDs having various sizes that is available for use in the plurality of CBDs. Also, the particular FBD having the first size has a lowest availability in the free pool of FBDs. Other methods, systems, and computer program products are described in accordance with additional embodiments.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 14, 2018
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9971692
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a plurality of access requests for data in the cache storage device, each request being directed to data in a common cache block descriptor (CBD). The CBD stores metadata corresponding to a storage location of the data in the cache storage device. The logic is also configured to update a request queue to reflect each access request from the plurality of access requests in an order in which individual access requests were received. Moreover, the logic is configured to delay at least some overlapping access requests.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9965390
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to select a cache block descriptor (CBD) from amongst a plurality of CBDs, the selected CBD including indications of being fragmented in the cache storage device. The logic is also configured to determine whether to defragment the selected CBD. Moreover, the logic is configured to defragment the selected CBD on the cache storage device in response to a decision to defragment the selected CBD.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9916249
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a write request including data to be written to the cache storage device. The logic is also configured to determine a size of the write request. Moreover, the logic is configured to select a chunk size from among a plurality of chunk sizes designated for storing data in the cache storage device. In addition, the logic is configured to allocate a fine block descriptor (FBD) having the selected chunk size to the write request.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9817757
    Abstract: In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9817713
    Abstract: One embodiment provides a method comprising, for at least one data block, selecting an erasure code from a plurality of erasure codes based on at least one property of the at least one data block and information relating to a data cache, and encoding, utilizing at least one hardware processor, the at least one data block with the selected erasure code. The information relating to the data cache includes cache space usage of the data cache.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, Mohit Saxena
  • Publication number: 20170228282
    Abstract: One embodiment provides a method comprising, for at least one data block, selecting an erasure code from a plurality of erasure codes based on at least one property of the at least one data block and information relating to a data cache, and encoding, utilizing at least one hardware processor, the at least one data block with the selected erasure code. The information relating to the data cache includes cache space usage of the data cache.
    Type: Application
    Filed: February 4, 2016
    Publication date: August 10, 2017
    Inventors: Aayush Gupta, Mohit Saxena
  • Publication number: 20170220281
    Abstract: In one general embodiment, a computer-implemented method includes creating multiple pools of micro services. Each of the pools includes a specific configuration set and resource properties. Also, the computer-implemented method includes receiving incoming workloads. Moreover, the computer-implemented method includes, for each of the incoming workloads, dynamically mapping the incoming workload, based on characteristics of the incoming workload, to an access path traversing a combination of a subset of the pools of micro services.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 3, 2017
    Inventors: Aayush Gupta, Dean Hildebrand, Nagapramod S. Mandagere, Mohit Saxena
  • Publication number: 20170185511
    Abstract: In various embodiments, techniques for improving function of in-memory processing systems include identifying data stored in a distributed filesystem, including data to be processed by an in-memory processing application and data not to be processed by the in-memory processing application; identifying one or more partitions of the data corresponding to the data to be processed; and selectively transferring the one or more partitions from the distributed filesystem to a memory of the in-memory processing application. Techniques may also include determining an average remote execution time of the in-memory processing system; tracking a waiting time of a job pending processing on a local node of the in-memory processing system; comparing the tracked waiting time of the job pending processing; and demoting a locality of the job if waiting time of the job exceeds the average remote execution time of the in-memory processing system. Corresponding systems and computer-program products are also disclosed.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventors: Lawrence Y. Chiu, Mohit Saxena, Erci Xu
  • Publication number: 20170139792
    Abstract: In one embodiment, a system includes a cache storage device, a back-end storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive indication of failure of a primary cache server at a secondary cache server, the primary and secondary cache servers being configured to manage read requests and write requests for the back-end storage device. The logic is also configured to set the secondary cache server to a by-pass mode for read requests directed to any portions of the back-end storage device managed by the primary cache server prior to the failure. Moreover, the logic is configured to read an index of cache block descriptors (CBDs) managed by the primary cache server prior to the failure into a memory of the secondary cache server.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170139830
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to select a cache block descriptor (CBD) from amongst a plurality of CBDs, the selected CBD including indications of being fragmented in the cache storage device. The logic is also configured to determine whether to defragment the selected CBD. Moreover, the logic is configured to defragment the selected CBD on the cache storage device in response to a decision to defragment the selected CBD.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170139829
    Abstract: In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena