Abstract: A system and method include a controller that reduces power dissipated by a switch, such as a source-controlled field effect transistor, when an estimated amount of power dissipated by the switch exceeds a predetermined threshold. Reducing the power dissipated by the switch prevents damage to the switch due to overheating. The controller determines the estimated amount of power dissipated by the switch using actual drain-to-source current and drain voltage data. In at least one embodiment, the controller includes a fail-safe, estimated power dissipation determination path that activates when the drain voltage data fails a reliability test. Additionally, in at least one embodiment, the controller includes a model of thermal characteristics of the switch. In at least one embodiment, the controller utilizes real-time estimated power dissipation by the switch and the model to determine when the estimated power dissipated by the switch exceeds a power dissipation protection threshold.

Abstract: An electronic system and method include a controller to operate in a start-up mode to accelerate driving a load to an operating voltage and then operates in a post-start-up mode. A start-up condition occurs when the controller detects that a load voltage is below a predetermined voltage threshold level. The predetermined voltage threshold level is set so that the controller will boost the voltage to an operating value of a load voltage at a faster rate than during normal, steady-state operation. The controller causes a switching power converter to provide charge to the load at a rate in accordance with a start-up mode until reaching an energy-indicating threshold. When the energy-indicating threshold has been reached, the controller causes the switching power converter to (i) decrease the amount of charge provided to the load relative to the charge provided during the start-up mode and (ii) operate in a distinct post-start-up-mode.

Abstract: A control system provides a control signal to a nonlinear plant that generates a response signal responsive to the control signal. The control system includes a detector that detects a predetermined value of a plant quantity, valley switching logic, coupled to the detector, to change a state of a plant switch when the plant quantity is minimized, and a pulse-width modulator, coupled to the valley switching logic, to generate a control signal that controls the plant switch. The valley switching logic includes a nonlinear delta-sigma modulator that compensates for an error in a plant response signal by adjusting the duration of an on-time of a plant switch to cause an average value of the plant response signal to converge toward a target signal value.

Abstract: In at least one embodiment, a lighting system receives an input signal, such as a supply voltage, that can be affected by a dimmer. The supply voltage can be affected by a dimmer when, for example, a dimmer phase cut (i.e. chopped) the supply voltage. A dimmer detection system of the lighting system determines if a dimmer is affecting the supply voltage. In at least one embodiment, the dimmer detection system also determines a type of the dimmer, such as detecting if the dimmer is a leading edge or trailing edge dimmer. In at least one embodiment, the dimmer detection system provides dimmer type data to one or more other circuits such as a switching power converter controller. The one or more other circuits utilize the dimmer type data to affect their operation.

Abstract: A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.