Abstract: The present invention generally relates to a virtual reality (VR) navigation system using artificial intelligence (AI), thus enabling providing of individualized and context-aware navigation experience in VR environments. It consists of an AI-inclusive central processing unit (CPU) that receives and processes real-time data from multiple hardware sensors deployed in a wearable VR headset, e.g., inertial measurement units (IMUs), eye-tracking sensors, biometric ones. This is AI-driven CPU that dynamically changes the navigation path and sensory outputs such as visual, audio, haptic based on user input/interaction & environmental context. It consists of a hand-held controller with numerous input interfaces and a wireless communication module, enabling it to be easily linked or integrated into several VR applications.

Abstract: Systems and methods are provided for obtaining raw mass spectrometry data from samples, determining signals present across the samples, determining a bin value to apply to the filtered mass spectrometry data, and after determining the bin value, generating an image-based representation of the raw mass spectrometry data, wherein the image-based representation indicates frequencies of peak intensities in each bin.

Abstract: A preferred method for providing multi-level security to a gate level information flow receives or specifies a security lattice having more than two security levels. The security lattice defines how security levels relate to each other. A hardware design implementing information flows including flows having security levels specified by the security lattice is received. Logic is created for testing the hardware design in view of the security lattice. A logic function is created based upon the hardware design and the logic for testing to implement the security lattice. Another method receives a hardware design in a hardware description language. At least a portion of the hardware design is synthesized to gate level primitives. Functional component tracking logic supporting more than two-security levels is built from the gate level primitives. Functional components in the hardware design are simulated with the functional component tracking logic.

Abstract: A method for detecting a timing channel in a hardware design includes synthesizing the hardware design to gate level. Gate level information flow tracing is applied to the gate level of the hardware design via a simulation to search for tainted flows. If a tainted flow is found, a limited number of traces are selected. An input on the limited number of traces is simulated to determine whether the traces are value preserving with respect to taint inputs, and to determine that a timing flow exists if the traces are value preserving with respect to the taint inputs.