Abstract: A heating device for testing a biological sample is disclosed. The heating device can include a heat source operable to generate heat. In addition, the heating device can include a controller in communication with the heat source and operable to control heat generation by the heat source to heat a biological sample at less than or equal to about 2 degrees C./s. Furthermore, a heating device for testing a biological sample is disclosed that can include a heat source operable to generate heat to heat a biological sample. The biological sample can be at least partially contained within a removable enclosure distinct from the heating device. Additionally, the heating device can include an enclosure interface associated with the heat source. The enclosure interface can be configured to interface with the enclosure such that heat is transferred from the heat source to the enclosure by conduction.

Abstract: The present disclosure is drawn to methods of preparing a saliva sample for loop-mediated isothermal amplification (LAMP) detection of a pathogen target. In some embodiments, such methods can include providing an amount of saliva from a test subject, and diluting the saliva in water to a degree that reduces a buffering capacity of the saliva while maintaining a sufficient concentration to allow for detection of the pathogen target.

Abstract: The present disclosure is drawn to compositions and methods for loop-mediated isothermal amplification (LAMP) analysis utilizing a pH-dependent output signal. The composition can comprise a pH sensitive dye, and a plurality of non-interfering LAMP reagents. The method can comprise providing an assembly of a solid phase medium and a composition, depositing a biological sample onto the solid phase medium, and heating the assembly to an isothermal temperature sufficient to facilitate a LAMP reaction.

Abstract: A liquid biological sample test cartridge is disclosed. The cartridge can include a tray. The cartridge can also include a chemical reaction pad supported by the tray. The cartridge can further include a chemical reaction pad cover disposed over the chemical reaction pad and coupled to the tray. The chemical reaction pad cover can have a sample opening to facilitate depositing a liquid biological sample at a predetermined location on the chemical reaction pad. In addition, the cartridge can include an outer cover operable to at least partially form an enclosure about the chemical reaction pad.

Abstract: Disclosed herein are methods for inducing immunity against a severe acute respiratory syndrome (SARS) coronavirus 2 (SARS-CoV2) in a patient in need thereof. The method comprises administering a vaccine composition comprising a self-adjuvanted SARS-CoV2 Spike (S) RNA-based vaccine (AAHI-SC2), followed by administering a replication defective adenovirus (hAd5) vaccine composition, wherein the adenovirus comprises an E1 gene region deletion and an E2b gene region deletion.

Abstract: A method and system for automatically reserving a room for a meeting is disclosed, in which a user is offered an option for enabling automatic room reservation during the creation of a scheduled meeting. The user can specify the time of the meeting, as well as preferences for the type of room that should be selected. The system can also ensure the availability of a suitable room for recurring meetings.

Abstract: Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract: A fault detection system for a fastener (224) in a machine (100) includes an ultrasonic sensor (404) that is integrated with the fastener and capable of emitting an ultrasonic signal (506) that travels through a length of the fastener (224). The ultrasonic sensor (404) receives a returning ultrasonic signal (506) and a processor (512) calculates a travel time between an emission of the ultrasonic signal (506) and a receipt of the returning ultrasonic signal (506). The processor (512) calculates an actual length (L) of the fastener (224) based on the travel time (510), compares the actual length (L) with a predetermined length of the fastener (224), and emits a wireless signal (519) to an electronic controller (612) of the machine (100) that is indicative of a structural state of the fastener (224).