Patents by Inventor Mohit

Mohit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10965278
    Abstract: Described is a high speed, low power level shifter circuit which includes a cross-coupled level shifter coupled to a sensing circuit. The sensing circuit turns off a cross-coupled node of a pair of cross-coupled nodes based on detecting that an input voltage has crossed a threshold voltage for a cross-coupled input transistor of a pair of cross-coupled input transistors, i.e. due to switching from a current logic level to an incoming logic level. Once the sensing circuit detects a threshold voltage crossing, a pull-up circuit pulls high a cross-coupled node and cross-coupled source transistor tied to the cross-coupled node. This turns off the cross-coupled source transistor and turns on another cross-coupled source transistor. Two parallel paths are now established to pull the cross-coupled node high, enabling a high-speed transition. The turning off of the cross-coupled source transistor also pulls the output to the incoming logic level.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 30, 2021
    Assignee: SiFive, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
  • Patent number: 10966059
    Abstract: A location tracking and distance monitoring system includes a plurality of portable transponders, each portable transponder having a wireless transmitter and configured to transmit location data, a location database storing the location data transmitted by the plurality of portable transponders, wherein each portable transponder is identified as a tag with co-ordinates in the location database, a distance monitoring module comprising at least one processor and configured via computer executable instructions to access the location data from the location database, define a coverage region with a coverage radius around each tag, determine overlapping zones of the coverage regions of the tags, and generate tag clusters based on the overlapping zones. Further, an associated method and computer readable medium are provided.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: March 30, 2021
    Assignee: Siemens Industry, Inc.
    Inventors: Mohit Dayal, Firas Khalil, Vikas Garg, Mark Egervari, Mohamad El Naamani, Clayton T. French, Artur Ottlik, Navneet Sharma, Malika Tandon
  • Patent number: 10966005
    Abstract: A telemetry manager receives, from a network server, global data collection information about network components in an optical network device. The global data collection information includes identifiers for network nodes in the network components from which telemetry data are to be collected, and reporting frequency and encoding format for sending collected telemetry data to the network server. The telemetry manager identifies, from the global data collection information, local data collection information specified for a network component, and sends this information to a telemetry agent in the network component. The telemetry manager receives telemetry data generated by a network node of the network component, where the data is provided according to instructions in the local data collection information. The telemetry manager converts the telemetry data from its native format to an encoding format specified by the global data collection information, and sends the encoded telemetry data to the network server.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignee: Infinera Corporation
    Inventors: Abhinava Sadasivarao, Sharfuddin Syed, Sachin Jain, Lu Biao, Ashok Kunjidhapatham, Anthony Jorgenson, Tjandra Trisno, Mana Palai, Biju Mathew, Mohit Misra, Balaji Gopalakrishnan
  • Patent number: 10963744
    Abstract: Approaches for automated fashion designing are described. A computer-implemented method for automated fashion designing includes: training, by a computer device, computer models using deep learning based computer vision; identifying, by the computer device, at least one gap using cognitively determined fashionability scores (F-scores); and creating, by the computer device, a new fashion design using the computer models and the at least one identified gap.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventor: Mohit Sewak
  • Patent number: 10963035
    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 30, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, James Lionel Panian, Richard Dominic Wietfeldt, Mohit Kishore Prasad, Amit Gil, Shaul Yohai Yifrach
  • Publication number: 20210092540
    Abstract: An audio system includes an H-bridge. The audio system implements one or more techniques for ensuring a transistor within the H-bridge does not turn on in the event of the detection of a short-circuit on the output of the H-bridge. Other transistors within the H-bridge can turn and thus audio can still be played to a speaker.
    Type: Application
    Filed: July 27, 2020
    Publication date: March 25, 2021
    Inventor: Mohit CHAWLA
  • Publication number: 20210090997
    Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Mohit K. HARAN, Reken PATEL, Richard E. SCHENKER, Charles H. WALLACE
  • Publication number: 20210090990
    Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Manish CHANDHOK, Richard E. SCHENKER, Florian GSTREIN, Leonard P. GULER, Charles H. WALLACE, Paul A. NYHUS, Curtis WARD, Mohit K. HARAN, Reken PATEL
  • Patent number: 10952754
    Abstract: The present invention provides a drill guide for orthopedic surgery. The drill guide is configured to facilitate drilling of a bone tunnel with a correct and repeatable placement. The drill guide is designed for drilling of the femoral bone during knee surgery. More particularly, in certain embodiments the drill guide is designed for ACL repair and replacement surgery. In a preferred embodiment of the present invention, the guide has 5 members: a center rail, a side rail, an anteromedial slider, a femoral slider, and a center pin.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 23, 2021
    Assignee: The Johns Hopkins University
    Inventors: Mohit Singhala, Matthew Lerner, Polly Charlene Ma, Andrew Jann, Rachel An, Bashir Ahmed Zikria
  • Patent number: 10957656
    Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Kyle Yazzie, Naga Sivakumar Yagnamurthy, Pramod Malatkar, Chia-Pin Chiu, Mohit Mamodia, Mark J. Gallina, Rajesh Kumar Neerukatti, Joseph Bautista, Michael Gregory Drake
  • Patent number: 10958609
    Abstract: One or more computing devices, systems, and/or methods for controlling a graphical user interface based upon a predicted messaging action of a messaging account are provided. For example, a plurality of messages associated with the messaging account may be received. Interactions with the plurality of messages may be tracked to generate sets of message interactions. The plurality of messages may be analyzed to identify sets of attributes. An expected action model may be generated based upon the sets of message interactions and the sets of attributes. Performance of a messaging action by a time threshold may be predicted based upon the expected action model. In response to a determination that the messaging action has not been performed by the time threshold, a reminder data structure may be generated. A graphical user interface may be controlled using the reminder data structure.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: March 23, 2021
    Assignee: Verizon Media Inc.
    Inventors: Mohit Goenka, Nikita Varma, Ashish Khushal Dharamshi
  • Patent number: 10956928
    Abstract: A method, computer program product, and computing system are provided for identifying an advertising opportunity on a first website in response to a user accessing the first website. Information associated with the user accessing the first website may be received. One or more digital advertisements of one or more fashion products from the second website may be provided for rendering on the first website based upon, at least in part, one or more fashion-ability scores representative of the one or more fashion products on the second website and the information associated with the user accessing the first website.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventor: Mohit Sewak
  • Patent number: 10956731
    Abstract: Techniques described herein implement heading identification and classification for a digital document in a digital medium environment. A document analysis system is leveraged to extract structural features from a digital document, identify heading candidates from among the structural features, validate the headings candidates, and classify validated headings into different headings types. The classified headings are then utilized to generate a sectioned version of the digital document (“sectioned document”) that is divided into different sections based on the headings. Further, a document directory is generated that includes the headings and that enables navigation to different sections of the sectioned document.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Adobe Inc.
    Inventors: Mohit Gupta, Uttam Dwivedi, Shawn Alan Gaither, Jayant Vaibhav Srivastava, Ashutosh Mehra
  • Patent number: 10956951
    Abstract: A crowd-sourced cloud environment allows for, and benefits from, modes of interaction between among the service providers (including the “resource providers” and the “cloud provider”) and consumers (also referred to herein as “tenants”) that are not practiced in a DC-centric cloud environment—specifically, the use of Internet-based social networking technology and Internet-based online marketplace technology to facilitate resource pooling and interaction between crowd-sourced cloud resource providers, the cloud provider, and crowd-sourced cloud consumers.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 23, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Plamen Nedeltchev, David Delano Ward, Alon Shlomo Bernstein, Mohit Agrawal
  • Publication number: 20210082798
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
  • Publication number: 20210077268
    Abstract: In one embodiment, an intervertebral implant includes a body and a locking element. The body includes a leading surface and a trailing surface opposite the leading surface. The body also includes first and second bone fastener passageways through the implant body and a cavity in between the first and second passageways. The cavity includes a trailing wall that separates the cavity from the trailing surface. The locking element is disposed in the cavity such that part of the locking element is visible through an access opening in the trailing wall so that the locking element may be rotated from outside of the implant. In a first rotational position, a first part of the locking element is located within one of the first and second passageways and in a second rotational position, the first part of the locking element is inside the body covered by the trailing wall.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 18, 2021
    Inventors: Jared Gordon Struck, Robert Clint Boyd, Dane Matthew Johannessen, Jennifer Anne Moore, Bryan D. Milz, Choll Kim, Alex Mohit, Yashar Javidan
  • Publication number: 20210082805
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Publication number: 20210081125
    Abstract: Embodiments are disclosed for a multi-tier storage system (MTSS). The techniques include identifying a first data extent stored in a first storage pool of MTSS based on a read-write heat mapping by the MTSS. The first data extent is associated with a mirrored volume. The first data extent is a mirrored copy of a second data extent stored in a second storage pool of the MTSS. The first storage pool is asymmetric to the second storage pool. The techniques also include determining that a second top promotion tier of the second storage pool is faster than a first top promotion tier of the first storage pool. The techniques further include promoting the second data extent to the second top promotion tier based on the determination. Additionally, the techniques include updating an I/O access policy to direct future I/O operations for the mirrored volume to the second data extent.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Kushal Patel, Mohit Chitlange, Sarvesh S. Patel, Ajinkya Nanavati
  • Patent number: 10951035
    Abstract: Systems, methods, and computer-readable media are described for addressing the unit commitment problem in a power grid by providing a communication-free control framework according to which each power generating unit in the power grid determines its own operating schedule for turning on or off based solely on local measurements.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 16, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ulrich Muenz, Xiaofan Wu, Mohit Sinha, Joachim Bamberger
  • Patent number: 10949604
    Abstract: Techniques described herein implement identifying artifacts in digital documents in a digital medium environment. A document analysis system is leveraged to extract page features from a digital document and to determine whether certain page features represent page artifacts such as headers and footers. Those page features determined to be page artifacts can be extracted from the digital document to generate a reflowed version of the digital document that preserves primary content. The primary content, for instance, is rearranged in the reflowed document to compensate for the extracted page artifacts.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 16, 2021
    Assignee: Adobe Inc.
    Inventors: Uttam Dwivedi, Mohit Gupta, Ashutosh Mehra