Abstract: Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a pre-test station having a height detection system configured to detect a height of a packaged IC when disposed therein prior to testing; a testing station for testing the packaged IC received from the pre-test station; and a device handler for moving the packaged IC to the testing station. In some embodiments, a method for testing packaged ICs may include detecting a height of a packaged IC to be tested disposed in a pre-test station; comparing the height to an expected height; and determining whether the detected height of the packaged IC is different than the expected height of the packaged IC by greater than or equal to a desired amount.

Abstract: Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a device handler for moving the packaged IC; a testing station for testing the packaged IC; and a pre-test conditioning station configured to remove at least a portion of an oxidation layer formed on contacts of the packaged IC prior to testing. In some embodiments, a method for testing packaged ICs may include providing a packaged IC to be tested; at least partially removing an oxidation layer from contacts of the packaged IC prior to testing; inserting the packaged IC into an interface structure; and testing the packaged IC.

Abstract: A socket for an integrated circuit is disclosed. The socket comprises a main body portion having a plurality of holes extending between a top surface and a bottom surface; an overlay positioned adjacent to the main body portion and having a plurality of holes corresponding to the plurality of holes of the main body portion, wherein the overlay comprises a plurality of conductors between holes; and a plurality of contact elements positioned in predetermined holes of the main body portion. A method of providing a connection in a socket is also disclosed.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: A protective mechanism for a probe card cover to prevent the probe card cover or attachment screws extending from the probe card cover from striking a wafer in a test system if the probe card is installed without removing the cover. The protective mechanism includes an elongate member that can be permanently attached to the probe card cover, or attached by screws to the probe card cover. The protective mechanism can be a bar that extends longer than an opening in a probe card holder tray through which probes of the probe card pass during testing. The bar can be hard, yet flexible enough to prevent damage to the probe card holder tray or probe card.

Abstract: A probe card configured for interchangeable heads. In one example, a probe card includes a probe card circuit board and a substrate. The substrate includes a first interface coupled to the probe card circuit board and a second interface having a plurality of die patterns. The plurality of die patterns are arranged with respect to the substrate in a plurality of probe pin configurations for a respective plurality of probe heads.

Abstract: A test system configuration is provided to enable testing of integrated circuit (IC) packages. The test system includes a test controller, an interface apparatus including a PC board with lines connecting the test controller to contact areas for contacting the IC packages and a handler for supporting the IC chips and interface apparatus to maintain electrical connections during testing. The handler includes docking plates for attaching to the PC board to provide a guide for the IC packages that are inserted in openings of the docking plates to align contacts of the IC packages and PC board. The docking plates are configured to provide quad (four) and octal (eight) test sites, with either the quad or octal docking plate mating to the same PC board and being supported in the same handler system. An alignment frame for mounting either the quad or octal docking plate is further provided as part of the handler.

Abstract: A standardized test head assembly for testing a plurality of integrated circuit dice each having a different bonding pad footprint, the test head assembly including an arrangement of probe holes defined by a predetermined configuration of contact positions, wherein the predetermined configuration defines each of the different bonding pad footprints so that during testing the probe holes align with a subset of the bonding pads for each of the different bonding pad footprints.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: Die probing devices can include multiple sets of probe wires, where certain probe wires correspond to test pads and other correspond to bond pads. The probe wires can be electrically coupled to each other using either a space transformer or a probe card, to provide appropriate continuity. Probe wires can generally be arranged in numerous different patterns depending upon (for example) pad layout, wire configuration, wire type, and probe head design/manufacturing constraints.

Abstract: A system for reducing condensation during testing of an integrated circuit is disclosed. An exemplary embodiment includes two seals which close both ends of an enclosed channel formed when the load board is secured to the device tester. Clean dry air with a pressure greater than that of the environment is feed into the enclosed channel and is trapped because of the seals.

Abstract: A hybrid interface apparatus including a fixed base including a contact-locking structure supporting several spring-based contact members, and a nesting member slidably positioned over the fixed base and having a central test area that includes an array of through-holes that are aligned with upper ends of the contact members. To facilitate testing of ICs including both relatively low-speed general-purpose I/O structures and new high-speed I/O structures, the contact members mounted on the contact structure include both low-cost, relatively high-inductance contact members for facilitating communication with the general-purpose I/O structures of the IC, and relatively expensive, low-inductance contact members for facilitating high-speed communications with the high-speed I/O structures of the IC.

Abstract: A hybrid interface apparatus including a fixed base including a contact-locking structure supporting several spring-based contact members, and a nesting member slidably positioned over the fixed base and having a central test area that includes an array of through-holes that are aligned with upper ends of the contact members. To facilitate testing of ICs including both relatively low-speed general-purpose I/O structures and new high-speed I/O structures, the contact members mounted on the contact structure include both low-cost, relatively high-inductance contact members for facilitating communication with the general-purpose I/O structures of the IC, and relatively expensive, low-inductance contact members for facilitating high-speed communications with the high-speed I/O structures of the IC.

Abstract: An interface structure includes first and second portions. The first portion has physical dimensions that are compatible with the docking area of an associated device tester, and includes a first socket configured to receive a first BGA package. The second portion, which is adjacent to and contiguous with the first portion, extends laterally beyond the docking area of the device tester to provide additional testing area that may include one or more additional sockets. In one embodiment, the second portion includes a second socket configured to receive a second BGA package, wherein the second size and configuration of second BGA package are different from the size and configuration of the first BGA package.

Abstract: A method and apparatus for testing parasitic effects on conducting paths in high-speed systems using a test package which allows for very accurate measurements of the parasitic effects to be taken. The test package is designed to be nearly identical to the actual IC package and has an external connector to allow measurements to be taken through the package, instead of at a point close to the package.

Abstract: An interface structure includes first and second portions. The first portion has physical dimensions that are compatible with the docking area of an associated device tester, and includes a first socket configured to receive a first BGA package. The second portion, which is adjacent to and contiguous with the first portion, extends laterally beyond the docking area of the device tester to provide additional testing area that may include one or more additional sockets. In one embodiment, the second portion includes a second socket configured to receive a second BGA package, wherein the second size and configuration of second BGA package are different from the size and configuration of the first BGA package.