Patents by Inventor Mohsen Purahmad

Mohsen Purahmad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735273
    Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: August 22, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Publication number: 20220148659
    Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Mohsen PURAHMAD, Chao-Han CHENG, Dongxiang LIAO, Bo LEI
  • Patent number: 11264104
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Patent number: 10996862
    Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Phil Reusswig, Mohsen Purahmad, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Publication number: 20200393973
    Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: Phil Reusswig, Mohsen Purahmad, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Publication number: 20200350025
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Mohsen PURAHMAD, Chao-Han CHENG, Dongxiang LIAO, Bo LEI
  • Patent number: 10741256
    Abstract: A data storage system may include a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. Methods are also described.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Publication number: 20200090760
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Mohsen PURAHMAD, Chao-Han CHENG, Dongxiang LIAO, Bo LEI
  • Patent number: 10573388
    Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mahim Raj Gupta, Mohsen Purahmad, Bo Lei, Joanna Lai, Xiying Costa
  • Publication number: 20190311770
    Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Mahim Raj Gupta, Mohsen Purahmad, Bo Lei, Joanna Lai, Xiying Costa
  • Patent number: 9805793
    Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 31, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Bijesh Rajamohanan, Juan Saenz, Alvaro Padilla, Mohsen Purahmad, Ashot Melik-Martirosian
  • Publication number: 20170287557
    Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Bijesh Rajamohanan, Juan Saenz, Alvaro Padilla, Mohsen Purahmad, Ashot Melik-Martirosian