Abstract: An apparatus includes a plurality of memory channels to a memory. The plurality of memory channels include a first slice and at least a second slice that is distinct from the first slice. The apparatus further includes power control circuitry coupled to the plurality of memory channels. The power control circuitry is configured to adjust, in accordance with a power collapse trigger condition associated with the first slice, operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice. The first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation.

Abstract: Various embodiments include methods and devices for implementing a scan dump of memory subsystem cores. Embodiments may include enabling a scan dump path of the memory subsystem during a computing device crash reset flow, the scan dump path comprising at least one memory controller having at least one scan dump logic module, a scan dump network on chip (NoC) module, and at least one scan dump data bus connecting the at least one scan dump logic module and the scan dump NoC, and initializing a scan mode for a memory path of the memory subsystem and for a low power memory path of the memory subsystem.