Patents by Inventor Moinuddin K. Qureshi
Moinuddin K. Qureshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220300849Abstract: A quantum computing method including: receiving program instructions; executing the program instructions on a quantum machine for a plurality of trials to generate a plurality of results; combining the plurality of results of the execution for each of the plurality of trials; and determining a program result of the execution based on the combination of the plurality of results.Type: ApplicationFiled: August 31, 2020Publication date: September 22, 2022Inventors: Swamit S. Tannu, Moinuddin K. Qureshi
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Patent number: 10068639Abstract: An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines.Type: GrantFiled: April 29, 2014Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Ashish Jagmohan, Moinuddin K. Qureshi, Luis A. Lastras
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Patent number: 10019370Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.Type: GrantFiled: July 1, 2016Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Bulent Abali, John S. Dodson, Moinuddin K. Qureshi, Balaram Sinharoy
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Patent number: 9846641Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.Type: GrantFiled: June 18, 2012Date of Patent: December 19, 2017Assignee: International Business Machines CorporationInventors: Michele Franceschini, Ashish Jagmohan, Moinuddin K. Qureshi, Luis A. Lastras
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Publication number: 20160314072Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.Type: ApplicationFiled: July 1, 2016Publication date: October 27, 2016Inventors: Bulent Abali, John S. Dodson, Moinuddin K. Qureshi, Balaram Sinharoy
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Patent number: 9424194Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.Type: GrantFiled: May 1, 2012Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Bulent Abali, John Dodson, Moinuddin K. Qureshi, Balaram Sinharoy
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Patent number: 9218296Abstract: A hybrid encryption scheme for storing data lines in a memory includes identifying data lines determined to be frequently accessed, and encrypting the data lines using a first encryption scheme. The hybrid encryption scheme also includes encrypting data lines determined not to be frequently accessed using a second encryption scheme.Type: GrantFiled: January 27, 2014Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Moinuddin K. A. Qureshi
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Publication number: 20150309941Abstract: An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: International Business Machines CorporationInventors: Michele M. Franceschini, Ashish Jagmohan, Moinuddin K. Qureshi, Luis A. Lastras
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Publication number: 20150212951Abstract: A hybrid encryption scheme for storing data lines in a memory includes identifying data lines determined to be frequently accessed, and encrypting the data lines using a first encryption scheme. The hybrid encryption scheme also includes encrypting data lines determined not to be frequently accessed using a second encryption scheme.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: International Business Machines CorporationInventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Moinuddin K. A. Qureshi
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Patent number: 9087612Abstract: Errors on a dynamic random access memory (“DRAM”) having an error correcting decoder (“ECC”) can be detected by the ECC when reading a row of the DRAM. The ECC includes error correcting code logic. If errors are detected that cannot be corrected by the ECC logic, test control logic determines weak cell information for the row, evaluates the errors using the weak cell information, and may correct the errors. The weak cell information may include weak cell locations and failure values.Type: GrantFiled: February 28, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Patent number: 9058896Abstract: A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.Type: GrantFiled: August 29, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-Hyoun Kim, Luis A. Lastras, Moinuddin K. Qureshi
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Patent number: 9037930Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.Type: GrantFiled: February 19, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Patent number: 8914764Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: GrantFiled: June 18, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Patent number: 8898544Abstract: This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.Type: GrantFiled: December 11, 2012Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Patent number: 8887014Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.Type: GrantFiled: December 11, 2012Date of Patent: November 11, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Patent number: 8874846Abstract: Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.Type: GrantFiled: September 14, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Ashish Jagmohan, John P. Karidis, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Patent number: 8863068Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: GrantFiled: June 18, 2012Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Patent number: 8848471Abstract: A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.Type: GrantFiled: August 8, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras, Moinuddin K. Qureshi
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Patent number: 8826216Abstract: A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.Type: GrantFiled: June 18, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Publication number: 20140195996Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: ApplicationFiled: June 18, 2012Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin