Abstract: Disclosed herein is a method of accessing a cache, the method comprising: mapping respective physical line addresses (PLAs) of a plurality of PLAs to respective cache locations of a plurality of cache locations in a cache, each PLA of the plurality of PLAs having an associated memory line; encrypting, with a block cipher using a first key, a first PLA of the plurality of PLAs to provide a first encrypted line address (ELA), the first ELA having an associated first encrypted cache location; upon receiving a request to access a first memory line associated with the first PLA, encrypting, using the first key, the first PLA into the first ELA to determine the associated first encrypted cache location; and accessing the first encrypted cache location. Also disclosed herein are systems for implementing the same.

Abstract: Disclosed herein are systems and methods for identifying and mitigating Flush-based cache attacks. The systems and methods can include adding a zombie bit to a cache line. The zombie bit can be used to track the status of cache hits and misses to the flushed line. A line that is invalidated due to a Flush-Caused Invalidation can be marked as a zombie line by marking the zombie bit as valid. If another hit, or access request, is made to the cache line, data retrieved from memory can be analyzed to determine if the hit is benign or is a potential attack. If the retrieved data is the same as the cache data, then the line can be marked as a valid zombie line. Any subsequent hit to the valid zombie line can be marked as a potential attack. Hardware- and software-based mitigation protocols are also described.

Abstract: A hybrid tracker system and method are disclosed for RH mitigation, which combines the best of both SRAM and DRAM to enable low-cost mitigation of RH at ultra-low thresholds. The system consists of two structures. First, an SRAM-based structure is provided that tracks aggregated counts at the granularity of a group of rows and is sufficient for the vast majority of rows, which receive only a few activations. Second, a per-row tracker stored in the DRAM-array is provided which can track an arbitrary number of rows; however, to limit performance overheads, this tracker is used only for the small number of rows that exceed the tracking capability of the SRAM-based structure.

Abstract: Disclosed herein are systems and methods for identifying and mitigating Flush-based cache attacks. The systems and methods can include adding a zombie bit to a cache line. The zombie bit can be used to track the status of cache hits and misses to the flushed line. A line that is invalidated due to a Flush-Caused Invalidation can be marked as a zombie line by marking the zombie bit as valid. If another hit, or access request, is made to the cache line, data retrieved from memory can be analyzed to determine if the hit is benign or is a potential attack. If the retrieved data is the same as the cache data, then the line can be marked as a valid zombie line. Any subsequent hit to the valid zombie line can be marked as a potential attack. Hardware- and software-based mitigation protocols are also described.

Abstract: Disclosed herein is a method of accessing a cache, the method comprising: mapping respective physical line addresses (PLAs) of a plurality of PLAs to respective cache locations of a plurality of cache locations in a cache, each PLA of the plurality of PLAs having an associated memory line; encrypting, with a block cipher using a first key, a first PLA of the plurality of PLAs to provide a first encrypted line address (ELA), the first ELA having an associated first encrypted cache location; upon receiving a request to access a first memory line associated with the first PLA, encrypting, using the first key, the first PLA into the first ELA to determine the associated first encrypted cache location; and accessing the first encrypted cache location. Also disclosed herein are systems for implementing the same.

Abstract: A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region.

Abstract: A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performance of the cache.