Abstract: An apparatus includes a poly current generator circuit, which includes a fractional bandgap circuit, or a bandgap voltage reference circuit and a current reference generator, an adaptive bias current generator, a frequency generator to generate an output clock signal having a select frequency, wherein the frequency generator includes a current starved ring oscillator that comprises n identical cascaded stages connected in a shape of a ring, wherein an output of the nth cascaded stage is fed back as an input of the first cascaded stage, wherein n is an odd number greater than or equal to 3; and clock buffers configured to buffer the output clock signal generated by the frequency generator for distribution.

Abstract: A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.

Abstract: A voltage regulator includes a load detection controller for detecting whether an output capacitor is present at an output of the voltage regulator; a digital controller for selecting a functional state of the voltage regulator based on a signal from the load detection controller; a first feedback loop for regulation when the output capacitor is not present; a second feedback loop for regulation when the capacitance output capacitor is present; and a first pass transistor shared by the load detection controller, the first feedback loop, and the second feedback loop, wherein the first pass transistor is configured to work with the first or second feedback loop selected for regulation based on the functional state of the voltage regulator.

Abstract: A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.

Abstract: An adaptive negative impedance system for improving power supply rejection (PSR) of a voltage regulator (VR) includes a variable negative impedance circuit with a control input; and a signal adjustment block (SAB), wherein a negative impedance value of the variable negative impedance circuit is dependent on a voltage regulator output current, and wherein the variable negative impedance circuit is a variable negative capacitance circuit and/or a variable negative resistance circuit, and the negative impedance value is a negative capacitance value and/or a negative resistance value.

Abstract: An automatically reconfigurable Buck-Boost DC-DC converter having an input supply and an output voltage includes a linear regulator (LDO) for Buck configuration; a switched-capacitor DC-DC converter; a capacitor and switch array, and a gain selector to switch between the linear regulator (LDO) when an output DC level is higher than an input DC level (Buck configuration) and the switched-capacitor DC-DC converter when the output DC level is lower than the input DC level (Boost configuration).

Abstract: A reference generation circuit includes a reference circuit and a local supply regulation circuit connected between an input supply and the reference circuit to supply a local regulated input to the reference circuit. The local supply regulation circuit comprises an error amplifier and a pass device, and wherein the error amplifier senses an output voltage of the pass device and an output voltage of the reference generation circuit to generate an output to control a gate terminal of the pass device.

Abstract: A method to adjust the load transient regulation of a low drop-out (LDO)/load switch linear voltage regulator (LVR) with an n-type pass element having an open loop transfer function, including determining during a load transient event if the gate of the pass—element goes lower than a scaled value of the output voltage or a constant voltage level, generating a control signal that controls a current sink block if the gate voltage of the pass element is lower than the output voltage, and enabling a current sink block that is controlled by the control signal and connecting the output of the current sink block to the output of the LVR.

Abstract: An architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture method support optionally determining during a power-up phase and by using a load detection circuit, the estimated load parameters that represents at least one selected from a group consisting of: the load time constant and the load resistor at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output load parameters, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is adjusted based on the estimated load parameters.

Abstract: Inrush current is a critical, undesirable behavior that results from the uncontrolled start-up or shut-down of voltage regulators. Large inrush currents lead to voltage overshoot at the output node of voltage regulators and this can damage the regulator load, in addition to peak current that can damage the packaging or the regulator itself. Embodiments of the invention introduce methods of inrush current reduction based on voltage reference generation. For example, one method is based on multiple filtered steps of the voltage reference for the voltage regulator. For example, another method is based on creating a voltage reference signal that has a continuous slope starting from zero and ending at zero. Embodiments of the invention reduce or limit the inrush current for sensitive applications.

Abstract: A method to adjust the load transient regulation of a low drop-out (LDO)/load switch linear voltage regulator (LVR) with an n-type pass element having an open loop transfer function, including determining during a load transient event if the gate of the pass—element goes lower than a scaled value of the output voltage or a constant voltage level, generating a control signal that controls a current sink block if the gate voltage of the pass element is lower than the output voltage, and enabling a current sink block that is controlled by the control signal and connecting the output of the current sink block to the output of the LVR.

Abstract: A soft-start/soft-stop (SS) controller for a voltage regulator. The SS controller includes a power up/down detector configured to perform at least one selected from a group consisting of detecting a power on condition of the voltage regulator to determine a start-up time period and detecting a power off condition of the voltage regulator to determine a shut-down time period, and a ramped reference voltage signal generator configured to perform at least one selected from a group consisting of increasing a voltage level of a ramped reference voltage signal using a pre-determined ramp-up rate during the start-up time period and decreasing the voltage level of the ramped reference voltage signal using a pre-determined ramp-down rate during the shut-down time period, wherein the ramped reference voltage signal is supplied to the voltage regulator for controlling an output voltage level of the voltage regulator.

Abstract: An architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture method support optionally determining during a power-up phase and by using a load detection circuit, the estimated load parameters that represents at least one selected from a group consisting of: the load time constant and the load resistor at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output load parameters, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is adjusted based on the estimated load parameters.

Abstract: A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

Abstract: A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

Abstract: A novel architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture and method also support optionally determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.