Patents by Inventor Mokhtar HIRECH

Mokhtar HIRECH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • AUTOMATIC CONFIGURATION OF PIPELINE MODULES IN AN ELECTRONICS SYSTEM
    Publication number: 20230325566
    Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Applicant: ARTERIS, INC.
    Inventors: Mokhtar HIRECH, Benoit de LESCURE
  • SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION
    Publication number: 20230101972
    Abstract: A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 30, 2023
    Applicant: ARTERIS, INC.
    Inventors: Mokhtar HIRECH, Benoit de LESCURE