Patents by Inventor Mon-Sen Lin

Mon-Sen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9524967
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Yeh Liu, Chien-Ming Lai, Yu-Ping Wang, Mon-Sen Lin, Ya-Huei Tsai, Ching-Hsiang Chiu
  • Patent number: 9379242
    Abstract: A method of fabricating a fin field effect transistor including providing a substrate having at least one fin structure, a dummy gate, and an internal dielectric layer thereon, removing the dummy gate to form a gate trench on the fin structure, blanketly forming a stress film on the substrate to cover a surface of the gate trench, performing a thermal annealing process, removing the stress film, and forming a metal gate is in the gate trench.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Mon-Sen Lin, Yu-Ping Wang, Yu-Ting Tseng, Hao-Yeh Liu, Chun-tsen Lu
  • Patent number: 9281374
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • Publication number: 20150004780
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 1, 2015
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • Patent number: 8872286
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 28, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • Publication number: 20130049141
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin