Patents by Inventor Mona Ebrish
Mona Ebrish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120201Abstract: A technique for selective-area diffusion doping of III-N epitaxial material layers and for fabricating power device structures utilizing this technique. Dopant species such as Mg are introduced into the III-N material layer and are diffused into the III-N material by annealing under stable or metastable conditions. The dopant species can be introduced via deposition of a metal or alloy layer containing such species using sputtering, e-beam evaporation or other technique known to those skilled in the art. The dopant material layer is capped with a thermally stable layer to prevent decomposition and out-diffusion, and then is annealed under stable or metastable conditions to diffuse the dopant into the III-N material GaN without decomposing the surface.Type: ApplicationFiled: March 31, 2023Publication date: April 11, 2024Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Travis J. Anderson, Mona A. Ebrish, Alan G. Jacobs, Karl D. Hobart, Francis J. Kub
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Publication number: 20230030549Abstract: A hybrid edge termination structure and method of forming the same. The hybrid edge termination structure in accordance with the invention is based on a junction termination extension (JTE) architecture, but includes an additional Layer of guard ring (GR) structures to further implement the implantation of dopants into the structure. The hybrid edge termination structure of the invention has a three-Layer structure, with a top Layer and a bottom Layer each having a constant dopant concentration in the lateral direction, and a middle Layer consisting of a plurality of spatially defined alternating regions that exhibit the electrical properties of either the top or bottom layer. By including the second layer, a discretized varying charge profile can be obtained that approximates the varying charge profile obtained using tapered edge termination but with easier manufacturing and lower cost.Type: ApplicationFiled: July 28, 2022Publication date: February 2, 2023Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Travis J. Anderson, Mona A. Ebrish, Andrew D. Koehler, Alan G. Jacobs, Matthew A. Porter, Karl D. Hobart, Prakash Pandey, Tolen Michael Nelson, Daniel G. Georgiev, Raghav Khanna, Michael Robert Hontz
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Patent number: 11569442Abstract: A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.Type: GrantFiled: June 17, 2020Date of Patent: January 31, 2023Assignee: International Business Machines CorporationInventors: Saba Zare, Michael Rizzolo, Mona A. Ebrish, Theodorus E. Standaert
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Publication number: 20210399212Abstract: A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.Type: ApplicationFiled: June 17, 2020Publication date: December 23, 2021Inventors: Saba Zare, Michael Rizzolo, Mona A. Ebrish, Theodorus E. Standaert
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Patent number: 11043494Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.Type: GrantFiled: July 2, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie, Deepika Priyadarshini, Indira Priyavarshini Seshadri, Nicole A. Saulnier
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Patent number: 11031250Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.Type: GrantFiled: November 29, 2018Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Mona A. Ebrish, Michael Rizzolo, Son Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi
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Patent number: 10818751Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.Type: GrantFiled: March 1, 2019Date of Patent: October 27, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger
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Patent number: 10811528Abstract: High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.Type: GrantFiled: March 21, 2018Date of Patent: October 20, 2020Assignee: International Business Machines CorporationInventors: Mona Ebrish, Xuefeng Liu, Brent Anderson, Huiming Bu, Junli Wang
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Patent number: 10804106Abstract: Techniques for providing a high temperature soft mask for semiconductor devices are described. In an embodiment, spin coating semiconductor device components with organic planarization material having a defined aromatic content aromatic content to provide an organic planarization layer. The method can further comprise ultra-fast annealing the organic planarization layer and forming an implanted or doped region in the semiconductor device. Three-dimensional FinFET components of a device can be spin coated with organic planarization material having high aromatic content, with the device cured at a first temperature. The organic planarization layer can be ultra-fast annealed at a second temperature that is greater than the first temperature. Aspects can include patterning the device, and forming an implanted or doped region in a semiconductor device.Type: GrantFiled: February 21, 2018Date of Patent: October 13, 2020Assignee: International Business Machines CorporationInventors: Mona Ebrish, Oleg Gluschenkov, Indira Seshadri, Ekmini Anuja De Silva
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Publication number: 20200279913Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger
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Patent number: 10734523Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.Type: GrantFiled: August 13, 2018Date of Patent: August 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
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Publication number: 20200176263Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Mona A. Ebrish, Michael Rizzolo, Son Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi
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Publication number: 20200052107Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.Type: ApplicationFiled: August 13, 2018Publication date: February 13, 2020Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
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Publication number: 20190326289Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: Lawrence A. CLEVENGER, Leigh Anne H. CLEVENGER, Mona A. EBRISH, Gauri KARVE, Fee Li LIE, Deepika PRIYADARSHINI, Indira Priyavarshini SESHADRI, Nicole A. SAULNIER
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Publication number: 20190296142Abstract: High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.Type: ApplicationFiled: March 21, 2018Publication date: September 26, 2019Inventors: Mona Ebrish, Xuefeng Liu, Brent Anderson, Huiming Bu, Junli Wang
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Publication number: 20190259616Abstract: Techniques for providing a high temperature soft mask for semiconductor devices are described. In an embodiment, spin coating semiconductor device components with organic planarization material having a defined aromatic content aromatic content to provide an organic planarization layer. The method can further comprise ultra-fast annealing the organic planarization layer and forming an implanted or doped region in the semiconductor device. Three-dimensional FinFET components of a device can be spin coated with organic planarization material having high aromatic content, with the device cured at a first temperature. The organic planarization layer can be ultra-fast annealed at a second temperature that is greater than the first temperature. Aspects can include patterning the device, and forming an implanted or doped region in a semiconductor device.Type: ApplicationFiled: February 21, 2018Publication date: August 22, 2019Inventors: Mona Ebrish, Oleg Gluschenkov, Indira Seshadri, Ekmini Anuja De Silva
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Patent number: 10388789Abstract: A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.Type: GrantFiled: December 5, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Mona A. Ebrish, Oleg Gluschenkov
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Patent number: 10381348Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.Type: GrantFiled: January 10, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie, Deepika Priyadarshini, Indira Priyavarshini Seshadri, Nicole A. Saulnier
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Patent number: 10361127Abstract: A method for forming a device with multiple gate lengths includes forming a gate stack on vertical fins. A cutting mask formed on the gate stack is etched to include two or more different heights. Gate structures with two or more gate lengths are etched by employing the two or more different heights in the cutting mask as an etch mask. The cutting mask is removed. A top source/drain regions is formed on top of the vertical fins.Type: GrantFiled: December 28, 2017Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Gauri Karve, Fee Li Lie, Indira Seshadri, Mona Ebrish, Leigh Anne H. Clevenger, Ekmini A. De Silva, Nicole A. Saulnier
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Publication number: 20190206738Abstract: A method for forming a device with multiple gate lengths includes forming a gate stack on vertical fins. A cutting mask formed on the gate stack is etched to include two or more different heights. Gate structures with two or more gate lengths are etched by employing the two or more different heights in the cutting mask as an etch mask. The cutting mask is removed. A top source/drain regions is formed on top of the vertical fins.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Gauri Karve, Fee Li Lie, Indira Seshadri, Mona Ebrish, Leigh Anne H. Clevenger, Ekmini A. De Silva, Nicole A. Saulnier