Abstract: Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.

Abstract: A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.

Abstract: A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

Abstract: A method of forming a semiconductor device using laser spike annealing is provided. The method includes providing a semiconductor substrate having a surface, forming a gate dielectric layer on the surface of the semiconductor substrate, laser spike annealing the gate dielectric layer, and patterning the gate dielectric layer and thus forming at least a gate dielectric. Source and drain regions are then formed to form a transistor. A capacitor is formed by connecting the source and drain regions.

Abstract: In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.

Abstract: Disclosed is a halogen-free resin composition comprising: (A) one or more phosphorus-containing epoxy resins; (B) a hardener; (C) a hardening accelerator; (D) a polyphenylene oxide resin; and (E) a filling material, wherein the hardener of component B has the structure represented by the following formula (I): wherein each symbol is as defined above. The halogen-free resin composition of the present invention without adding halogen has excellent heat resistance and flame retardant property, and excellent dielectric property. The halogen-free resin composition of the present invention is particularly useful in the application of bonding sheets, composite materials, laminated plates, printed circuit boards, copper foil adhesives, inks used for build-up process, semiconductor packaging materials and the like.

Abstract: Disclosed is a halogen-free resin composition comprising: (A) one or more phosphorus-containing epoxy resins; (B) a hardener; (C) a hardening accelerator; (D) a polyphenylene oxide resin; and (E) a filling material, wherein the hardener of component B has the structure represented by the following formula (I): 1

Abstract: The new thionyl phosphazene polymers, which contain recurring structural units corresponding to the following formula ##STR1## are prepared by ring-opening polymerization of cyclothionyl chlorophosphazene corresponding to the following formula ##STR2## at temperatures of 100.degree. to 300.degree. C. in the presence of an inert organic solvent and reaction of the polymer thus obtained, which corresponds to the following formula ##STR3## with salts corresponding to the following formulaM(R.sup.1 -R.sup.5)in the presence of an inert organic solvent at temperatures of 20.degree. to 200.degree. C.The new thionyl phosphazene polymers may be used for the production of thermoplastics, elastomers or thermosets.