Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

Abstract: The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semiconductor device. The process includes doping a single crystal substrate with a first dopant type, baking the doped single crystal substrate at a temperature less than 900° C., and at a pressure less than 100 torr; and depositing the SiGe layer on the baked single crystal substrate (epi SiGe) to serve as the base electrode and on the STI region (poly SiGe) to serve as a connection for the base electrode. The semiconductor device is thereby created from the combination of the doped single crystal substrate and the deposited SiGe layer.

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract: A method of forming a silicon nitride-silicon dioxide composite insulator layer for use as a gate insulator stack for an MOSFET device, has been developed. The method features formation of the silicon dioxide component of the gate insulator stack, after formation of the overlying silicon nitride component, allowing the gate insulator stack to be comprised with a nitrogen profile presenting enhanced barrier characteristic and less interface charge than counterpart silicon nitride-silicon dioxide composites formed wherein the silicon nitride component was deposited on an already grown underlying silicon dioxide layer. Oxygen ions, or oxygen radicals obtained via ultra-violet procedures, penetrate the silicon nitride component and locate in a top portion of the semiconductor substrate. Subsequent annealing allows reaction of the oxygen ions or radicals with a top portion of the semiconductor substrate resulting in the desired silicon dioxide component underlying silicon nitride.

Abstract: Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.

Abstract: The present disclosure provides a method for forming and manufacturing a silicon germanium (SiGe) based device. After forming a substrate of the device and forming one or more layers of semiconductor processing materials in one or more predetermined locations to establish an opening for depositing one or more SiGe material layers, a pre-baking process is applied to the device under a low pressure not to exceed 79 torr and 900° C. Once completed, the one or more SiGe material layers are deposited and other conventional steps are taken to complete the manufacturing of the device.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication.

Abstract: An embodiment for a method for forming a self-passivated copper interconnect structure. An insulating layer is formed over a semiconductor structure. An opening is formed in the insulating layer. Next, we form a fill layer comprised of Cu and Ti over insulating layer. In a nitridation step, we nitridize the fill layer to form a self-passivation layer comprised of titanium nitride over the fill layer.

Abstract: A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.

Abstract: A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.

Abstract: An apparatus and method for controllably etching a semiconductor wafer fabricated by a semiconductor processing system. Generally, an etcher is associated with the semiconductor processing system, such that etcher includes one or more electrodes thereof. An electrode position monitor can then be utilized for monitoring a position of the electrode, thereby permitting an adjustable size control of the etch head, which is controllable according to an associated etching recipe. The etch head is generally moveable according to a step mode. Such an arrangement thus increases wafer uniformity and precision process control during wafer fabrication and etching.

Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

Abstract: Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.

Abstract: A gas distribution system for improving asymmetric etching and deposition control over a substrate diameter in a plasma reactor including a plasma reactor chamber further including a substrate holder for holding a substrate surface disposed in a lower portion of said plasma reactor; at least one gas distributor disposed within the plasma reactor chamber for distributing reactant gases where at least one gas distributor including a plurality of gas feed zones in communication with at least one gas source for selectively delivering a gas flow independently to at least one of the plurality of gas feed zones.

Abstract: A gas distribution system for improving asymmetric etching and deposition control over a substrate diameter in a plasma reactor including a plasma reactor chamber further comprising a substrate holder for holding a substrate surface disposed in a lower portion of said plasma reactor; at least one gas distributor disposed within the plasma reactor chamber for distributing reactant gases said at least one gas distributor including a plurality of gas feed zones in communication with at least one gas source for selectively delivering a gas flow independently to at least one of the plurality of gas feed zones.

Abstract: A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric layer. A doped silicon semiconductor substrate is covered with variable thickness silicon oxide regions on the surface thereof with junctions between the variable thickness regions. The silicon oxide regions are substantially thicker beneath the center of the floating gate electrode. Source/drain regions formed in the substrate extend beneath the tunnel oxide regions with the junctions aligned with the regions. The floating gate electrodes formed over the silicon oxide regions above the source/drain regions including dielectric sidewalls within the floating gate electrode above the junctions. The variable thickness silicon oxide regions are tunnel oxide regions on either side of a gate oxide region.

Abstract: A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.

Abstract: A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer.

Abstract: A method of forming a Flash EEPROM device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about −10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 Å to about 120 Å.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication.