Patents by Inventor Mong-Sup Lee
Mong-Sup Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10957647Abstract: Integrated circuit (IC) devices are provided. An IC device includes a substrate including an active region. The IC device includes a bit line on the substrate. The IC device includes a direct contact connected between the active region and the bit line. The IC device includes a contact plug on the substrate. Moreover, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact.Type: GrantFiled: March 19, 2019Date of Patent: March 23, 2021Inventors: Dong-kak Lee, Yoon-ho Son, Mong-sup Lee, Wook-yeol Yi
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Publication number: 20200051921Abstract: Integrated circuit (IC) devices are provided. An IC device includes a substrate including an active region. The IC device includes a bit line on the substrate. The IC device includes a direct contact connected between the active region and the bit line. The IC device includes a contact plug on the substrate. Moreover, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact.Type: ApplicationFiled: March 19, 2019Publication date: February 13, 2020Inventors: Dong-kak Lee, Yoon-ho Son, Mong-sup Lee, Wook-yeol Yi
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Patent number: 10297495Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: GrantFiled: April 2, 2018Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
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Patent number: 10290537Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: GrantFiled: January 5, 2017Date of Patent: May 14, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
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Publication number: 20180226290Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing atType: ApplicationFiled: April 2, 2018Publication date: August 9, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Mong-sup LEE, Sang-jun LEE, Yoon-ho SON
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Publication number: 20170133262Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing atType: ApplicationFiled: January 5, 2017Publication date: May 11, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Mong-sup LEE, Sang-jun LEE, Yoon-ho SON
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Patent number: 9570316Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: GrantFiled: May 21, 2015Date of Patent: February 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
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Patent number: 9390961Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.Type: GrantFiled: September 10, 2014Date of Patent: July 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-Sup Lee, Byoung-Yong Gwak, Byung-Ho Kwak, Yoon-Kyung Kim, Tae-Joon Park, Byung-Sul Ryu, In-Seak Hwang
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Publication number: 20150340250Abstract: A wet etching nozzle, semiconductor manufacturing equipment including the same, and a wet etching method using the same are provided. The wet etching nozzle includes a first supply pipe configured to supply a first solution, for etching a partial area of an etched layer, to a substrate including the etched layer; a first suction pipe configured to suck the first solution from the substrate; a second supply pipe configured to supply a second solution for cleaning the partial area of the etched layer; and a second suction pipe configured to suck the second solution from the substrate.Type: ApplicationFiled: December 5, 2014Publication date: November 26, 2015Inventors: Mong-Sup LEE, Dong-Gyun HAN, Jong-Hyuk PARK
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Publication number: 20150340281Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: ApplicationFiled: May 21, 2015Publication date: November 26, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mong-sup LEE, Sang-jun LEE, Yoon-ho SON
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Publication number: 20150171163Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Inventors: Mong-Sup LEE, Byoung-Yong GWAK, Byung-Ho KWAK, Yoon-Kyung KIM, Tae-Joon PARK, Byung-Sul RYU, In-Seak HWANG
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Patent number: 8723297Abstract: In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.Type: GrantFiled: July 7, 2011Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Ho Son, Mong-Sup Lee, In-Seak Hwang, Dae-Hyuk Chung, Suk-Hun Choi, Sang-Jun Lee
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Publication number: 20120025283Abstract: In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.Type: ApplicationFiled: July 7, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Ho Son, Mong-Sup Lee, In-Seak Hwang, Dae-Hyuk Chung, Suk-Hun Choi, Sang-Jun Lee
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Publication number: 20100173470Abstract: In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked.Type: ApplicationFiled: January 8, 2010Publication date: July 8, 2010Inventors: Mong-Sup Lee, In-Seak Hwang, Keum-Joo Lee, Jin-Hye Bae, Bo-Wo Choi, Seung-Jae Lee
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Publication number: 20080188049Abstract: Methods of manufacturing non-volatile memory devices are provided including sequentially forming a tunnel insulating layer, a charge-trapping layer, a blocking layer and a conductive layer on a substrate having a channel region. The conductive layer is patterned to form a word line structure, and the blocking layer and the charge-trapping layer are etched using an aqueous acid solution as an etching solution to form a blocking layer pattern and a charge-trapping layer pattern.Type: ApplicationFiled: January 30, 2008Publication date: August 7, 2008Inventors: Woo Gwan Shim, Mong-Sup Lee, Ji-Hoon Cha, Chang-Ki Hong, Kun-Tack Lee
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Publication number: 20080044971Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming an etch stop layer on a substrate, forming a mold layer on the substrate, and forming an opening exposing the substrate by patterning the mold layer and the etch stop layer, wherein the opening includes a lower portion defined by the etch stop layer and a middle portion. The method further includes enlarging the lower portion by etching a side portion of the etch stop layer exposed by the opening using an etching solution including sulfuric acid and water; and forming a lower electrode on an inner surface of the opening including the enlarged lower portion, wherein, after enlarging the lower portion, a width of the lower portion is greater than a width of the middle portion.Type: ApplicationFiled: August 2, 2007Publication date: February 21, 2008Applicant: SAMSUNG ELECTRONICS CO,. LTD.Inventors: Dae-Hyuk KANG, Chang-Ki HONG, Kun-Tack LEE, Im-Soo PARK, Dong-Gyun HAN, Mong-Sup LEE, Jung-Min OH
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Publication number: 20070254425Abstract: Example embodiments of the present invention relates to methods of fabricating a semiconductor device. Other example embodiments of the present invention relate to methods of fabricating a semiconductor device using a metal nitride layer as a gate electrode. The methods may include providing a semiconductor substrate having a first region and a second region. A gate insulating layer, a metal nitride layer and/or an amorphous carbon layer may be sequentially formed on the substrate. The amorphous carbon layer may be selectively etched, forming an amorphous carbon mask covering the first region. The metal nitride layer, exposed by the amorphous carbon mask, may be etched, forming a preliminary metal nitride pattern. The amorphous carbon mask may be removed.Type: ApplicationFiled: January 18, 2007Publication date: November 1, 2007Inventors: Sang-Yong Kim, Mong-Sup Lee, Chang-Ki Hong, Woo-Gwan Shim