Abstract: A method for simulating faults in integrated circuits of electronic systems implementing applications under functional safety includes operating a simulation step of the system or electronic circuit on a processing system and executing the application under functional safety. The simulation step has a fault injection procedure including injecting a set of faults during simulation in determined locations, and verifying if observation points and diagnostic points connected to determined root failure modes are perturbed. The simulation step includes before the injecting step during simulation in determined locations of an electronic circuit performing a procedure to select a set of effective faults, pertaining only to effective root failure modes, which allow obtainment of the overall diagnostic coverage target, and supplying the set of effective faults for the execution of the injecting step during simulation in determined locations of the electronic circuit.

Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.

Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.