Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.

Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.

Abstract: Embodiments of the present disclosure include techniques for transferring non-power of two (2) bytes of data between modules of an integrated circuit over an on-chip communication fabric. In one embodiment, the present disclosure includes an on-chip communication fabric, a first module comprising an interface coupled to the fabric having a first data width, and a second module comprising an interface coupled to the fabric having a second data width smaller than the first data width. The non-power of two (2) bytes of data are sent between the first and second modules through the fabric, and the fabric maps the non-power of two (2) bytes of data between the first and second data widths.

Abstract: Embodiments of the present disclosure include techniques for transferring non-power of two (2) bytes of data between modules of an integrated circuit over an on-chip communication fabric. In one embodiment, the present disclosure includes an on-chip communication fabric, a first module comprising an interface coupled to the fabric having a first data width, and a second module comprising an interface coupled to the fabric having a second data width smaller than the first data width. The non-power of two (2) bytes of data are sent between the first and second modules through the fabric, and the fabric maps the non-power of two (2) bytes of data between the first and second data widths.

Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: A method of determining a motion value for a missing pixel in an interlaced video field using an adaptive window. The method includes computing a first mean absolute difference (MAD) value for a pixel based on a 1×5 window, computing a second MAD value for the pixel using a 3×5 window, and selectively blending the first and second MAD values to form a resultant motion value.

Abstract: A recursive motion detector for detecting motion in an interlaced video signal. The motion detector includes a first frame motion detector receiving a next field and a first previous field, a second frame motion detector receiving a current field and a second previous field, and a third frame motion detector receiving a next field and a third previous field. Motion is detected when the first, second and third frame motion detectors combine to produce a frame motion result.

Abstract: According to aspects of embodiments, a method of determining an aperture window in a video deinterlacer includes: computing a first mean absolute difference (MAD) value for a pixel based on a 1×5 window; computing a second MAD value for the pixel using a 3×5 window; and selectively blending the first and second MAD values to form a resultant motion value.

Abstract: A recursive motion detector, comprises: a first frame motion detector receiving a next field and a first previous field; a second frame motion detector receiving a current field and a second previous field; and a third frame motion detector receiving a next field and a third previous field; wherein motion is detected when the first, second and third frame motion detectors combine to produce a frame motion result.

Abstract: A system and method for processing a digital video signal corresponding to an image are provided. A plurality of independent edge detecting processes or edge detector modules detect a set of edges and at least one additional edge that is not included in the set of edges. An edge map includes data regarding all edges identified by any edge detecting process or module, and a visually perceptible artifact of the image is altered based at least in part on an evaluation of the edge map. The system and method detects and filters block artifacts and ringing or other noise from digital images, resulting in reduced image distortion.

Abstract: A method and apparatus of image processing is disclosed. The method and apparatus accomplish image processing by separating a luma component and a chroma component of an image signal. Averaging of at least some of the image pixels of the luma component is done over a plurality of image pixels to provide a plurality of surround function values. Retinex-like processing of the luma component is done using the surround function values to provide a Retinex-like processed luma component. The Retinex-like processed luma component is added to the chroma component of the image signal to provide a processed image signal.

Abstract: A recursive motion detector, comprises: a first frame motion detector receiving a next field and a first previous field; a second frame motion detector receiving a current field and a second previous field; and a third frame motion detector receiving a next field and a third previous field; wherein motion is detected when the first, second and third frame motion detectors combine to produce a frame motion result.

Abstract: According to aspects of embodiments, a method of determining an aperture window in a video deinterlacer includes: computing a first mean absolute difference (MAD) value for a pixel based on a 1×5 window; computing a second MAD value for the pixel using a 3×5 window; and selectively blending the first and second MAD values to form a resultant motion value.

Abstract: A system and method for processing a digital video signal corresponding to an image are provided. A plurality of independent edge detecting processes or edge detector modules detect a set of edges and at least one additional edge that is not included in the set of edges. An edge map includes data regarding all edges identified by any edge detecting process or module, and a visually perceptible artifact of the image is altered based at least in part on an evaluation of the edge map. The system and method detects and filters block artifacts and ringing or other noise from digital images, resulting in reduced image distortion.