Patents by Inventor Monica Mathur
Monica Mathur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160133691Abstract: Steps are taken to ensure that the bulk dielectric layer exhibits a crystalline phase before the deposition of a second electrode layer. The crystalline phase of the bulk dielectric layer facilitates the crystallization of the second electrode layer at lower temperature during a subsequent anneal treatment. In some embodiments, one or more interface layers are inserted between the bulk dielectric layer and the first electrode layer and/or the second electrode layer. The interface layers may act as an oxygen sink, facilitate the crystallization of the electrode layer at lower temperature during a subsequent anneal treatment, or provide barriers to leakage current through the film stack.Type: ApplicationFiled: November 6, 2014Publication date: May 12, 2016Inventors: Prashant B. Phatak, Hanhong Chen, Tony P. Chiang, Chien-Lan Hsueh, Monica Mathur
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Publication number: 20160111471Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.Type: ApplicationFiled: October 16, 2014Publication date: April 21, 2016Inventors: Monica Mathur, Mark Clark
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Patent number: 9318531Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.Type: GrantFiled: October 16, 2014Date of Patent: April 19, 2016Assignee: Intermolecular, Inc.Inventors: Monica Mathur, Mark Clark
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Publication number: 20160099304Abstract: A capacitor stack includes a base bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. A molybdenum nitride or a molybdenum oxy-nitride layer is formed above the dielectric layer. A fourth top electrode layer is formed above the third top electrode layer. The base top electrode layer includes a conductive metal nitride material.Type: ApplicationFiled: October 6, 2014Publication date: April 7, 2016Inventor: Monica Mathur
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Patent number: 8962354Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.Type: GrantFiled: September 19, 2014Date of Patent: February 24, 2015Assignee: Intermolecular, Inc.Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
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Publication number: 20150010705Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.Type: ApplicationFiled: September 19, 2014Publication date: January 8, 2015Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
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Patent number: 8865484Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.Type: GrantFiled: December 26, 2012Date of Patent: October 21, 2014Assignee: Intermolecular, Inc.Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
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Publication number: 20140179033Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: INTERMOLECULAR, INC.Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
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Patent number: 8551851Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.Type: GrantFiled: May 4, 2011Date of Patent: October 8, 2013Assignee: Intermolecular, Inc.Inventors: Hanhong Chen, Pragati Kumar, Sunil Shanker, Edward Haywood, Sandra Malhotra, Imran Hashim, Nobi Fuchigami, Prashant Phatak, Monica Mathur
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Publication number: 20110203085Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Applicant: INTERMOLECULAR, INC.Inventors: Hanhong Chen, Pragati Kumar, Sunil Shanker, Edward Haywood, Sandra Malhotra, Imran Hashim, Nobi Fuchigami, Prashant Phatak, Monica Mathur
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Patent number: 7968452Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.Type: GrantFiled: June 30, 2009Date of Patent: June 28, 2011Assignee: Intermolecular, Inc.Inventors: Hanhong Chen, Pragati Kumar, Sunil Shanker, Edward Haywood, Sandra Malhotra, Imran Hashim, Nobi Fuchigami, Prashant Phatak, Monica Mathur
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Publication number: 20100330269Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Hanhong Chen, Pragati Kumar, Sunil Shanker, Edward Haywood, Sandra Malhotra, Imran Hashim, Nobi Fuchigami, Prashant Phatak, Monica Mathur