Abstract: A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

Abstract: A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

Abstract: A method for forming a self-aligned bipolar transistor structure uses the selective growth of a doped silicon emitter in a sloped oxide emitter window to form the self-aligned structure. In an alternate process flow, the top emitter layer is SiGe with a high Ge content that is etched off selectively after deposition of the extrinsic base layer. In another alternate flow, a nitride plug formed on top of the emitter blocks the extrinsic base implant from the emitter region.

Abstract: The low-voltage, e.g., 2.5-volt, transistors that support the logic operations of a CMOS device are formed to have a thin layer of gate oxide, while the high-voltage, e.g., 3.3 or 5-volt, transistors that support the analog operations of the device are formed to have a thick layer of gate oxide in a cost-effective process flow that requires only one additional masking step over a conventional double-poly CMOS process.

Abstract: Disclosed are MOSFET devices in which a region extends from the drain and is, self-aligned with the gate. The region has a lower dopant concentration than the drain. The presence of the extension region substantially enhances breakdown voltage while not adding excessive on-resistance for the devices.

Abstract: Fabrication of a high frequency bipolar transistor structure is integrated into a CMOS process flow with minimal additional cost. The polysilicon emitter of the bipolar device and the polysilicon gate of the MOS device use separate polysilicon layers and, therefore, allow the bipolar emitter and the MOS gate to be doped independently of each other. The process scheme does not require the MOS device to be subdivided.