Abstract: An apparatus, including: a set of one or more cores; a processor configured to generate a proposed frequency of a clock signal provided to the set of one or more cores in accordance with a dynamic clock voltage scaling (DCVS); a feedback-based clock frequency adjuster configured to generate an adjustment frequency based on feedback information from the set of one or more cores; and a clock generator configured to generate the clock signal with an effective frequency based on the proposed frequency and the adjustment frequency.