Abstract: An embodiment semiconductor device includes a first die package component, a second interposer electrically coupled to a first side of the first die package component, a third interposer having a voltage regulator circuit electrically coupled to a second side of the first die package component, and an optical component and a high-bandwidth-memory die, each electrically coupled to the second interposer. The first die package component may further include a double-sided semiconductor die, such that a first side of the double-sided semiconductor die is electrically coupled to the second interposer, and a second side of the double-sided semiconductor die is electrically coupled to the third interposer. The first die package component may further include a molding material and a through-molding-via formed in the molding material, such that the through-molding-via provides an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.

Abstract: A device includes a semiconductor chip and a redistribution layer (RDL) structure connected to the semiconductor chip. The redistribution layer structure comprises a first region including: a first bump connected to the semiconductor chip; a second bump; and a plurality of first redistribution layers connected between the first bump and the second bump. The RDL structure includes a second region laterally surrounding the first region, the second region including a plurality of second redistribution layers. The RDL structure includes an isolation region laterally separating the plurality of first redistribution layers from the plurality of second redistribution layer. The isolation region includes at least one region that is straight, continuous, extends from an upper surface of the redistribution layer structure to a lower surface of the first redistribution layer structure, and has at least a selected width.

Abstract: A method includes switching a receiver path network of a front-end module to a first matching mode in a receive mode. The method further includes switching a transmitter path network of the front-end module to a first resonance mode in the receive mode. The method further includes switching the transmitter path network to a second matching mode in a transmit mode. The method further includes switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: A method includes switching a receiver path network of a front-end module to a first matching mode in a receive mode. The method further includes switching a transmitter path network of the front-end module to a first resonance mode in the receive mode. The method further includes switching the transmitter path network to a second matching mode in a transmit mode. The method further includes switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a connecting element, a first semiconductor device, a second semiconductor device, a first underfill layer, and a package layer. The interposer substrate is disposed on the carrier substrate. The connecting element is disposed in the interposer substrate. The connecting element includes a dielectric element and first conductive features disposed in the dielectric element. The first semiconductor device and the second semiconductor device are disposed on the interposer substrate. The first semiconductor device is electrically connected to the second semiconductor device through the connecting element. The first underfill layer is disposed between the first semiconductor device, the second semiconductor device, and the interposer substrate. The package layer surrounds the first semiconductor device, the second semiconductor device, and the first underfill layer.

Abstract: Devices and methods of manufacture for a hybrid interposer including a molding structure within a semiconductor device. A semiconductor device may include a semiconductor die, a package substrate, and a hybrid interposer positioned between the semiconductor die and the package substrate. The hybrid interposer may include a molding material layer, and an integrated device positioned within the molding interposer layer. The hybrid interposer may further include an organic material layer, and a non-organic material layer. The molding material layer may include an epoxy molding compound (EMC). The organic material layer may include a dielectric polymer material. The non-organic material layer may include a silicon-based dielectric material.

Abstract: Devices and methods of manufacture for a hybrid interposer within a semiconductor device. A semiconductor device may include a package substrate and a hybrid interposer. The hybrid interposer may include an organic interposer material layer, and a non-organic interposer material layer positioned between the organic interposer material layer and the package substrate. The semiconductor device may further include an integrated device positioned within the hybrid interposer. In one embodiment, the integrated device may be positioned within the organic interposer material layer. In another embodiment, the integrated device may be positioned within the non-organic interposer material layer. In a further embodiment, the integrated device may be positioned within the organic interposer material layer and the non-organic interposer material layer.

Abstract: A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.

Abstract: An interposer may include a first metal trace located on a first dielectric layer, a second dielectric layer located on the first dielectric layer, a line-shaped via located in the second dielectric layer and connected to the first metal trace, and a second metal trace located on the second dielectric layer and connected to the line-shaped via.

Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: A method includes placing a device die and a pre-formed dielectric block over a first carrier, encapsulating the device die and the pre-formed dielectric block in an encapsulating material, grinding a top side of the encapsulating material to expose the top side of the pre-formed dielectric block, removing the carrier from the encapsulating material, the pre-formed dielectric block, and the device die to reveal a bottom side of the pre-formed dielectric block, and forming a ground panel, a feeding line, and a patch on the encapsulating material. The ground panel, the feeding line, the patch, and the pre-formed dielectric block form a patch antenna.

Abstract: A method includes switching a receiver path network of a front-end module to a first matching mode in a receive mode. The method further includes switching a transmitter path network of the front-end module to a first resonance mode in the receive mode. The method further includes switching the transmitter path network to a second matching mode in a transmit mode. The method further includes switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.

Abstract: A method includes (a) switching a receiver path network of a front end module to a first matching mode in a receive mode. The method further includes (b) switching a transmitter path network of the front end module to a first resonance mode in the receive mode. The method further includes (c) switching the transmitter path network to a second matching mode in a transmit mode. The method further includes (d) switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

Abstract: A method includes (a) switching a receiver path network of a front end module to a first matching mode in a receive mode. The method further includes (b) switching a transmitter path network of the front end module to a first resonance mode in the receive mode. The method further includes (c) switching the transmitter path network to a second matching mode in a transmit mode. The method further includes (d) switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.