Patents by Inventor Monte F. Mar
Monte F. Mar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6753739Abstract: A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.Type: GrantFiled: December 20, 2002Date of Patent: June 22, 2004Assignee: Cypress Semiconductor Corp.Inventors: Monte F. Mar, Warren A. Snyder
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Patent number: 6515551Abstract: An oscillator circuit configured to generate an output signal having a frequency comprising a current source, a trim circuit, and one or more capacitors. The current source may be configured to generate a temperature independent current in response to a first adjustment signal. The trim circuit may be configured to generate the first adjustment signal. The one or more capacitors may be configured to charge to a controlled voltage using the temperature independent current. The controlled voltage may regulate a variation of the frequency of the output signal.Type: GrantFiled: November 22, 2000Date of Patent: February 4, 2003Assignee: Cypress Semiconductor Corp.Inventors: Monte F. Mar, Warren A. Snyder
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Patent number: 6466072Abstract: An apparatus for combining stages of a multiplexer and a mixer into a single stage. The apparatus provides a first circuit configured to generate a first output signal in response to (i) one or more a input signals and (ii) one or more first select signals, a second circuit configured to generate a second output signal in response to (i) one or more a input signals and (ii) one or more second select signals, and a first and second mix signal configured to provide a third output signal in response to the first and second output signals. The third output signal provides a portion of the first and second output signals controlled by the first and second mix signals.Type: GrantFiled: March 30, 1998Date of Patent: October 15, 2002Assignee: Cypress Semiconductor Corp.Inventor: Monte F. Mar
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Patent number: 6373306Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.Type: GrantFiled: October 12, 2000Date of Patent: April 16, 2002Assignee: Cypress Semiconductor Corp.Inventors: Eric N. Mann, Galen E. Stansell, Monte F. Mar
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Patent number: 6294962Abstract: A current source and a load circuit. The oscillator circuit may be configured to present an output signal having a frequency in response to (i) a current, (ii) a load, and (iii) an input signal. The current source may be configured to generate the current in response to one or more first control signals. The load circuit may be configured to generate the load in response to one or more second control signals.Type: GrantFiled: December 9, 1998Date of Patent: September 25, 2001Assignee: Cypress Semiconductor Corp.Inventor: Monte F. Mar
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Patent number: 6191660Abstract: A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.Type: GrantFiled: March 24, 1999Date of Patent: February 20, 2001Assignee: Cypress Semiconductor Corp.Inventors: Monte F. Mar, Warren A. Snyder
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Patent number: 6175259Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.Type: GrantFiled: February 9, 1999Date of Patent: January 16, 2001Assignee: Cypress Semiconductor Corp.Inventors: Eric N. Mann, Galen E. Stansell, Monte F. Mar
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Patent number: 6114914Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal having a first frequency in response to (i) an input having a second frequency and (ii) a first control signal. The second circuit may be configured to generate the second frequency in response to (i) a plurality of third clock signals and (ii) a second control signal. The third circuit may be configured to present the first and second control signals in response to one of said plurality of third clock signals.Type: GrantFiled: May 19, 1999Date of Patent: September 5, 2000Assignee: Cypress Semiconductor Corp.Inventor: Monte F. Mar
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Patent number: 5900752Abstract: A circuit and method for deskewing signals by using cross power supply logic paths to compensate for delays created by power supplies operating at different voltages. A first replica circuit operating at a first supply voltage is placed in series with a first signal operating at a second supply voltage. A second replica circuit operating at the second supply voltage is placed in series with a second signal having a skew difference from the first signal and operating at the first supply voltage. The replica circuits generally have a scale factor which is generally a fraction of the equivalent driver circuits associated with the particular output signals. As a result, the present invention will deskew arbitrary power supply differences. By matching delays, the replica and true circuits provide the same delay. As a result, the sum of the delays for all the blocks in each path will be constant which maintains a desired skew difference between the output signals.Type: GrantFiled: January 24, 1997Date of Patent: May 4, 1999Assignee: Cypress Semiconductor Corp.Inventor: Monte F. Mar
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Patent number: 5892383Abstract: Two voltage controlled resistance elements are coupled together in parallel. The first voltage controlled resistance element is coupled to a first voltage input, a voltage source, and an output. The second voltage controlled resistance element is coupled to a second voltage input, the voltage source, the first voltage controlled resistance element, and the output. The parallel resistance elements provide a variable resistance based on the resistance values of the first and second voltage controlled resistance elements.Type: GrantFiled: September 27, 1996Date of Patent: April 6, 1999Assignee: Intel CorporationInventor: Monte F. Mar
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Patent number: 5822387Abstract: A clock synthesizer is disclosed that includes a phase-locked loop circuit having two modes of operation: a non-slewing mode of operation, and a frequency-slewing mode of operation. During the power-up of the system, the PLL is controlled to operate in the non-slewing mode of operation to effect rapid variations in the output frequency. A power-on reset circuit is disclosed which determines when the system is in the power-up interval, and generates a power-on-reset signal to so indicate. The PLL operates in a frequency-slewing mode after power-up to provide controlled transitions in the frequency of the output reference signal of the PLL. A phase-locked loop circuit having structure to implement both modes is provided, as well as an adjustable lock detector circuit. The output of the lock detector, a logical lock signal, is used to enable the frequency-slewing mode of the PLL circuit.Type: GrantFiled: March 25, 1996Date of Patent: October 13, 1998Assignee: Cypress Semiconductor CorporationInventor: Monte F. Mar
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Patent number: 5724007Abstract: A lock detector suitable for detecting when an output signal of a phase-locked loop circuit is phase-locked to an input reference signal. The lock detector includes a pair of delay lines, that are adjustable, which are used to create a window signal around the reference clock signal. UP and DOWN signals from the PLL circuit are fed to an OR gate to generate an actual out-of-lock signal. When the PLL circuit is phase-locked within an acceptable phase error range, the UP, and DOWN signals, if any, will appear within the generated window signal. When the PLL circuit is not phase-locked within the acceptable phase error range, the UP, and DOWN signals occur outside of the window. The window signal, and the output of the OR gate are connected to an AND gate to generate a gated out-of-lock signal. The gated out-of-lock signal is connected to a switched-capacitor charge pump.Type: GrantFiled: March 25, 1996Date of Patent: March 3, 1998Assignee: Cypress Semiconductor CorporationInventor: Monte F. Mar
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Patent number: 5532636Abstract: A charge pump circuit suitable for use in a high frequency phase locked loop. The charge pump circuit comprises a biasing circuit, a charging transistor, a discharging transistor, and a pair of complementary switches. The charging transistor may be a p-channel field effect transistor (FET), and the discharging transistor may be a matched n-channel FET. The drains of the charging and discharging transistors are coupled together to form an output node for the charge pump circuit, and the biasing circuit provides a biasing voltage to the gates of the charging and discharging transistors. A first complementary switch is coupled in series between a supply voltage VCC and the source of the charging transistor. Similarly, a second complementary switch is coupled in series between system ground VSS and the source of the discharging transistor.Type: GrantFiled: March 10, 1995Date of Patent: July 2, 1996Assignee: Intel CorporationInventors: Monte F. Mar, Paul D. Madland