Abstract: The subject matter described herein includes a camera sensor with event token based image capture and reconstruction. The sensor includes a photodetector for capturing light from a portion of a scene and for producing a signal indicative of the light. An integrator is coupled to the photodetector for accumulating charge resulting from the signal output by the photodetector and can be reset each time the charge reaches a predetermined level. An in-pixel processor is coupled to the integrator for resetting the integrator and generating an event token each time the predetermined level of charge is accumulated. A communication pipeline communicates the event tokens for downstream processing. A postprocessor is coupled to the pipeline for receiving the event tokens and for determining output intensity for the portion of the scene being reconstructed based on a number of reset events and a time between at least two of the event tokens.

Abstract: The subject matter described herein includes a camera sensor with event token based image capture and reconstruction. The sensor includes a photodetector for capturing light from a portion of a scene and for producing a signal indicative of the light. An integrator is coupled to the photodetector for accumulating charge resulting from the signal output by the photodetector and can be reset each time the charge reaches a predetermined level. An in-pixel processor is coupled to the integrator for resetting the integrator and generating an event token each time the predetermined level of charge is accumulated. A communication pipeline communicates the event tokens for downstream processing.

Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.

Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.

Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.

Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.

Abstract: Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous application specific integrated data pipeline circuits with preemption includes a plurality of modular circuit stages that are connectable with each other and with other circuit elements to form multi-stage asynchronous application specific integrated data pipeline circuits for asynchronously sending data and tokens in a forward direction through the pipeline and for asynchronously sending anti-tokens in a backward direction through the pipeline. Each stage is configured to perform a handshaking protocol with other pipeline stages, the protocol including receiving either a token from the previous stage or an anti-token from the next stage, and in response, sending both a token forward to the next stage and an anti-token backward to the previous stage.

Abstract: Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous application specific integrated data pipeline circuits with preemption includes a plurality of modular circuit stages that are connectable with each other and with other circuit elements to form multi-stage asynchronous application specific integrated data pipeline circuits for asynchronously sending data and tokens in a forward direction through the pipeline and for asynchronously sending anti-tokens in a backward direction through the pipeline. Each stage is configured to perform a handshaking protocol with other pipeline stages, the protocol including receiving either a token from the previous stage or an anti-token from the next stage, and in response, sending both a token forward to the next stage and an anti-token backward to the previous stage.

Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.

Abstract: An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the request signal indicates the arrival of a distinct new data item. Each stage comprises a data latch that is normally enabled to allow data to pass through, and a latch controller that enables and disables the data latch. The request signal and the data are inputs to the data latch. Once the stage has latched the data, a done signal is produced, which is sent to the latch controller, to the previous stage as an acknowledgment signal, and to the next stage as a request signal. The latch controller disables the latch upon receipt of the done signal, and re-enables the data latch upon receipt of the acknowledgment signal from the next stage. For correct operation, the request signal must arrive at the stage after the data inputs have stabilized.

Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.

Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.

Abstract: An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the request signal indicates the arrival of a distinct new data item. Each stage comprises a data latch that is normally enabled to allow data to pass through, and a latch controller that enables and disables the data latch. The request signal and the data are inputs to the data latch. Once the stage has latched the data, a done signal is produced, which is sent to the latch controller, to the previous stage as an acknowledgment signal, and to the next stage as a request signal. The latch controller disables the latch upon receipt of the done signal, and re-enables the data latch upon receipt of the acknowledgment signal from the next stage. For correct operation, the request signal must arrive at the stage after the data inputs have stabilized.

Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.

Abstract: A latchless dynamic asynchronous digital pipeline uses control information for a processing stage from the subsequent processing stage as well as stages further down the pipeline. A first function block in a first processing stage is enabled to enter a first evaluate phase and a first precharge phase in response to a first precharge control signal provided by a second, subsequent processing stage which is asserted upon completion of evaluation by the second processing stage and a second precharge control provided by a third processing stage which is asserted upon completion of evaluation by the third processing stage, such that the first evaluate phase is enabled by at least one of the de-assertion of the first precharge control signal and the assertion of the second precharge control signal, and such that the first precharge phase is enabled by the assertion of the first precharge control signal and the de-assertion of the second precharge control signal.

Abstract: A latchless dynamic asynchronous digital pipeline uses control information for a processing stage from the subsequent processing stage as well as stages further down the pipeline. A first function block in a first processing stage is enabled to enter a first evaluate phase and a first precharge phase in response to a first precharge control signal provided by a second, subsequent processing stage which is asserted upon completion of evaluation by the second processing stage and a second precharge control provided by a third processing stage which is asserted upon completion of evaluation by the third processing stage, such that the first evaluate phase is enabled by at least one of the de-assertion of the first precharge control signal and the assertion of the second precharge control signal, and such that the first precharge phase is enabled by the assertion of the first precharge control signal and the de-assertion of the second precharge control signal.