Abstract: A liquid crystal display panel includes first and second substrates being bonded by a sealant, and an elastic barrier formed between the first and second substrates inside the sealant, the elastic barrier and the sealant having a distance therebetween.

Abstract: A thin film transistor (TFT) substrate includes: a plurality of gate wirings; a plurality of data wirings insulatedly crossing the gate wirings to define a plurality of pixels; a plurality of common voltage lines formed along edges of pixels and mutually connected in an extending direction of the gate wirings; and a plurality of common electrodes formed at the pixel such that the plurality of common electrodes partially overlap with the common voltage line and mutually connected in an extending direction of the data wirings. A uniform common voltage can be stably applied on the entire surface of the TFT substrate.

Abstract: A liquid crystal display device includes first and second substrates, gate and data lines formed on the first substrate and crossing each other to define a pixel region, a first common electrode in a first part of the pixel region, the first common electrode having a plate shape, a plurality of first pixel electrodes directly over the first common electrode and at a first fixed interval in the first part of the pixel region, a second pixel electrode alternately arranged with a second common electrode at a second fixed interval in a second part of the pixel region, and a layer of liquid crystal molecules between the first and second substrates.

Abstract: A pixel electrode structure of a display device is discussed. According to an embodiment, the pixel electrode structure includes a plurality of sub pixel electrodes disposed substantially in parallel in the pixel region, wherein the sub pixel electrodes have progressively greater widths and progressively greater spaces therebetween starting from one side of the pixel region to the other opposite side of the pixel region.

Abstract: An array substrate for a liquid crystal display device, includes: a gate line and a data line on a substrate, the data line crossing the gate line to define a pixel region; an insulating layer between the gate line and the data line; a switching element adjacent to a crossing of the gate line and the data line; a pixel electrode connected to the switching element, the pixel electrode disposed in the pixel region; and a first buffer pattern at a first side of one of the gate line and the date line and overlapped with the other one of the gate line and the date line, the first buffer pattern being disposed at the same layer as the one of the gate line and the date line.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

Abstract: A manufacturing method of an array substrate for a liquid crystal display device includes among other features, preparing a substrate including a display area and a non-display area, forming first and second gate shorting bars in the non-display area and electrically connected to gate lines, forming first and second data shorting bars in the non-display area and electrically connected to data lines, forming n gate probe test lines in the non-display area, forming m data probe test lines in the non-display area, forming first connection patterns connecting the gate lines and the n gate probe test lines, and forming second connection patterns connecting the data lines and the m data probe test lines, wherein the gate lines include n gate groups connected to the n gate probe test lines, respectively, and wherein the data lines include m data groups connected to the m data probe test lines, respectively.