Patents by Inventor Moo Joon SHIN

Moo Joon SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240036478
    Abstract: Provided is a lithography model simulation method. The method comprises receiving a first mask image, generating a second mask image by simulating an optical model on the first mask image, generating at least one third mask image by simulating a quenching model on the second mask image, and generating a resist image by performing machine learning on the first mask image, the second mask image, and the third mask image. The generating of the resist image comprises outputting first output data by convolving the first mask image with a first kernel, outputting second output data by convolving the second mask image with a second kernel, outputting third output data by convolving the third mask image with a third kernel, and adding together the first to third output data. Each of the first to third kernels is or includes a free-form kernel.
    Type: Application
    Filed: July 11, 2023
    Publication date: February 1, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han Veen KOH, Soo Yong LEE, Moo-Joon SHIN, Kyoung Yoon PARK
  • Patent number: 10852645
    Abstract: In a method for minimizing optical proximity correction errors in a semiconductor pattern. The method includes modifying a mask in a quantized unit to reduce an edge placement error between a simulation layout shape and a target layout shape; adjusting a critical dimension (CD) error between a CD of the simulation layout shape and a CD of the target layout shape to generate an adjusted CD error by further modifying at least one side of the mask in a predetermined unit; and reforming the simulation layout shape by modifying each side of the mask with arbitrary correction values.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moo Joon Shin, Kyung Jae Park
  • Publication number: 20200124980
    Abstract: In a method for minimizing optical proximity correction errors in a semiconductor pattern. The method includes modifying a mask in a quantized unit to reduce an edge placement error between a simulation layout shape and a target layout shape; adjusting a critical dimension (CD) error between a CD of the simulation layout shape and a CD of the target layout shape to generate an adjusted CD error by further modifying at least one side of the mask in a predetermined unit; and reforming the simulation layout shape by modifying each side of the mask with arbitrary correction values.
    Type: Application
    Filed: May 1, 2019
    Publication date: April 23, 2020
    Inventors: Moo Joon SHIN, Kyung Jae PARK