Patents by Inventor Moo-Kyung Lee

Moo-Kyung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240177114
    Abstract: Provided are a system for business process automation and a method thereof. The system according to some embodiments may include a connect manager configured to register and manage application programming interface (API) information for services, a process execution engine configured to execute a target business process comprising a particular service task, which is a task using a particular service provided by a service module, and a connect broker configured to acquire API information for the particular service, registered through the connect manager, during execution of the target business process in response to a request from the process execution engine, and process the particular service task by sending a request for the particular service to the service module using the acquired API information.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 30, 2024
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Young Sik JUNG, Moo Young CHO, Kang Hyeok LEE, Hyong Gook KIM, In Yong JANG, Chul Ho CHOI, Jeong Heon KIM, Ho Kyung YOO, Yeong Ho LEE, Kyung Ho CHO, Tae Jin HWANG, Jung Hee YOON, Hee Jong KIM
  • Publication number: 20240167711
    Abstract: The simulation system for predicting heating and cooling loads of a building comprises the collection unit collecting measurement data of a target building from a BEMS, the identification unit identifying indoor and outdoor temperature, humidity, and insolation measured in the building in real time based on RTS method, the correlation derivation unit deriving a correlation between energy usage based on the BEMS measurement data collected by the collection unit and the cooling and heating loads according to indoor and outdoor temperature, humidity, and insolation identified by the identification unit, the simulation unit predicting a change in cooling and heating loads according to a change in at least one of pieces of measurement data based on the correlation derived from the correlation derivation unit to perform a simulation, and the information provision unit providing a simulation result from the simulation unit in a visible form to a user terminal.
    Type: Application
    Filed: September 19, 2023
    Publication date: May 23, 2024
    Inventors: Tae Dong LEE, Won Jang PARK, Min Ho CHOI, Soo Hyun YANG, Moo Kyung SEO, Han Sung CHOI, Hye Mi LIM, Ji Hun PARK, So Jeong PARK, Ki Bum HAN, Hyeong Jae JEON
  • Patent number: 11915513
    Abstract: Provided are an apparatus for performing leveling of a person image and an operating method thereof. The method includes: receiving an original person image; selecting an arbitrary latent vector in a latent space; generating a virtual person image based on the latent vector; optimizing the latent vector such that identity similarity between the original person image and the virtual person image increases; manipulating the optimized latent vector; and generating a levelled person image corresponding to the original person image, by using the manipulated latent vector.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 27, 2024
    Assignees: NCSOFT CORPORATION, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seoungyoon Kang, Min Jae Kim, Moo Kyung Song, Hyunjung Shim, Gun Hee Lee
  • Patent number: 10325058
    Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moo-Kyung Lee, Jaeick Son, Sunghoon Kim
  • Publication number: 20170329889
    Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.
    Type: Application
    Filed: February 27, 2017
    Publication date: November 16, 2017
    Inventors: MOO-KYUNG LEE, JAEICK SON, SUNGHOON KIM
  • Patent number: 8878253
    Abstract: A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Kim, Hwa-Kyung Shin, Moo-Kyung Lee, Jong-Ho Lim
  • Publication number: 20110303965
    Abstract: A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.
    Type: Application
    Filed: May 3, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Soo Kim, Hwa-Kyung Shin, Moo-Kyung Lee, Jong-Ho Lim