Abstract: Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivation

Abstract: A package for a power semiconductor device is made using the method comprising the steps of preparing a lead frame including a blade or paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus.

Abstract: A micro light valve which is corresponding to each of pixels for display and which passes or shuts a light beam by electrostatic force to display images, said light valve comprising a data electrode formed on a substrate and connected with each of data lines through a via; a selection electrode formed on the substrate and connected with each of selection lines; a common electrode formed between the selection and data electrodes; a flat-shaped micro shifting element capable of moving in linear direction and which serves as a resistance body; insulating layers formed respectively between the shifting element and each of the electrodes; a frame for serving as a black matrix, which has a guiding means for guiding the shifting element; and the three electrodes for receiving externally applied driving signals to drive the shifting element and which serve as stationary elements with three phases.

Abstract: Disclosed is a switch circuit which has a depletion mode n-channel MOSFET which can be used in a circuit allowing only a positive voltage to be supplied thereto, comprising a first D-FET having a gate for receiving an input signal, a drain for outputting an output signal and a source; a first resistor connected between the drain of the first D-FET and a positive voltage source to bias the drain of the first D-FET; a second D-FET having a gate connected to an intermittence controlling voltage source, a drain and a source connected to the positive voltage source and the source of the first D-FET 201, respectively; a second resistor connected between the gate of the second D-FET and a ground to bias the gate of the second D-FET; a constant-current source connected between each of the sources of the first and second D-FET and the ground; a bypass capacitor connected in parallel with the constant-current source and between the drain of the constant-current source and the ground to bypass an RF signal to the ground

Abstract: A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic packa

Abstract: A method is disclosed for manufacturing a very fast micro light valve of the type used to control the passage of light through a pixel. The method comprises preparing a substrate, which can be made of glass, and forming transparent electrodes on the main surface of the substrate. Next an insulating layer is deposited on the substrate and a first sacrificial layer is formed on the insulating layer. A pattern shifting element layer is formed on the first sacrificial layer and a second sacrificial layer is formed on the substrate and provided with a shifting element layer. After portions of the sacrificial layers are removed by etching to form a frame contact portion, a patterned frame layer is formed on the frame contact portion. Then a frame and a shifting element capable of moving in the frame under an applied external electrostatic force are formed by removing the remaining sacrificial layers.

Abstract: There is disclosed a semiconductor device having a plurality of chips in which a predetermined extended addresses are allocated for each of the chips to select the chips in a multiple-chip module, the device comprising: a plurality of semiconductor chip selectors equipped in said semiconductor device, for supplying an internal chip select signals to select the chips in response to said extended addresses and a module select signal; and each of said semiconductor chip selectors having a plurality of decoders for receiving the extended addresses and outputting a predetermined logic signal, and an AND gate for receiving said module select signal and said logic signal of each of said decoders and outputting said internal chip select signals.