Abstract: A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.

Abstract: The present invention relates to an electrode forming method in circuit devices such as boards and chip devices, and a chip package and multilayer board using the same, in particular, in which protective bumps and an insulation layer are provided in terminal areas of a circuit device and then the protective bumps are removed to obtain via holes so that electrodes may be formed for electrical connection with other circuit elements.

Abstract: A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first substrate arranged on the first surface of the chip and having a first conductive via hole connected to the first terminal, a second substrate arranged on the second surface of the chip and having at least one second conductive via hole connected to the second terminal, and a resin molding part formed around the chip between the first substrate and the second substrate. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.

Abstract: A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.

Abstract: A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first substrate arranged on the first surface of the chip and having a first conductive via hole connected to the first terminal, a second substrate arranged on the second surface of the chip and having at least one second conductive via hole connected to the second terminal, and a resin molding part formed around the chip between the first substrate and the second substrate. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.