Abstract: A semiconductor package device has a circuit board with upper and lower conductive metal patterns respectively formed on upper and lower surfaces of the circuit board, a cavity centrally formed in the lower surface, and an opening through the upper surface that is connected to the cavity. A semiconductor chip is attached to the lower surface of the circuit board by an adhesive so that bonding pads of the chip are exposed through the opening. The semiconductor chip is disposed entirely within the cavity of the circuit board. Plating layers formed on side surfaces of the circuit board are electrically interconnected to the upper and lower metal patterns. An encapsulant protects the electrical interconnection parts of the semiconductor device package.

Abstract: A multichip package having individual chips which can be tested at the package level. A first pattern of conductive wires is formed on an upper surface of the circuit board for electrically connecting the individual chips. A second pattern of conductive wires is formed on the upper surface of the circuit board for providing data connections between the individual chips. Common pads formed in the circuit board extend from the upper surface to a lower surface of the circuit board, and the second patten of conductive wires is connected via the common pads. A molding compound is formed over the upper surface of the circuit board, embedding the individual chips and the first and second conductive patterns, while leaving the lower surface of the circuit board and a lower surface of the common pads exposed. A test socket having pad contact pins corresponding to the locations of the common pads, is placed at the lower surface of the circuit board so that signals may be applied and detected at common pads.