Abstract: A method of arranging a memory cell array in a semiconductor memory device, comprising the steps of dividing the memory cell array into a plurality of memory cell array areas having equal size, providing within the memory cell array a plurality of sub-normal memory cell arrays and at least one redundant memory cell array, arranging the plurality of sub-normal memory cell arrays and the at least one redundant memory cell array into the plurality of memory cell array areas, and arranging a plurality of sub-normal word line drivers, such that each sub-normal word line driver is adjacent to one of the plurality of memory cell array areas.

Abstract: A half Vcc generating circuit generates an accurate half supply voltage with high driving power. The half Vcc generating circuit includes a bias circuit supplied with an internal supply voltage and a driving circuit supplied with an external supply voltage. The internal supply voltage is independent of and lower than the external supply voltage.

Abstract: Disclosed is a semiconductor device with redundancy for replacing a memory cell with a predetermined defect with additional spare cells. In a semiconductor memory device having a plurality of normal submemory arrays, the present invention discloses a redundancy technique that allows any redundant address decoder to be used with any of the submemory arrays. This maximizes efficiency in redundant repairs as well as maximizes the use of the chip area.

Abstract: A semiconductor memory device includes a refresh timer for generating a refresh clock pulse, a binary counter for generating a predetermined number of signals of different frequencies and a circuit for generating a self-refresh enable signal in response to the signal transmitted from the binary counter. A back-bias clock pulse generator is also included having first, second and third selectors, of which the third selector selects one of the signals transmitted from the binary counter in response to a signal output from each of the first and second selectors. A back-bias generator having an oscillator and a back-bias voltage detecting circuit and a selection circuit for receiving the output signal from the back-bias voltage detection circuit is attached thereto. A signal is transmitted to the oscillator in response to the self-refresh enable signal.