Abstract: A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Abstract: A master for transmitting data to a slave via a bus segment by segment is provided. The master includes a finite state machine (FSM) configured to receive and analyze dirty bits for first data segments to be included in a current segment among the data and to output a first selection signal and location information related to the current segment according to an analysis result and a first multiplexer configured to determine whether to output the current segment as a dirty data segment to the bus based on the first selection signal.

Abstract: A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Abstract: A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Abstract: A memory controller, a memory system managing refresh operations for respective banks and an operating method of the memory controller are provided. The operating method of the memory controller includes determining the banks requested for access by analyzing an address, selecting at least one bank predicted to be accessed based on the determination result, setting a refresh order of the banks according to the selecting result, and controlling refresh operations for the banks according to the set order.

Abstract: A master for transmitting data to a slave via a bus segment by segment is provided. The master includes a finite state machine (FSM) configured to receive and analyze dirty bits for first data segments to be included in a current segment among the data and to output a first selection signal and location information related to the current segment according to an analysis result and a first multiplexer configured to determine whether to output the current segment as a dirty data segment to the bus based on the first selection signal.

Abstract: A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Abstract: A cache controller includes an entry list determination module and a cache replacement module. The entry list determination module is configured to receive a quality of service (QoS) value of a process, and output a replaceable entry list based on the received QoS value. The cache replacement module is configured to write data in an entry included in the replaceable entry list. The process is one of a plurality of processes, each having a QoS value, and the replaceable entry list is one of a plurality of replaceable entry lists, each including a plurality of entries and each corresponding to one of the QoS values. The number of total entries is allocated to processes based on the QoS values of the processes.

Abstract: A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address signal, and a write permission signal. The storage unit writes and stores input data, in response to the first control signal. The write permission signal is received from an external source and indicates whether to protect the written data.

Abstract: A register updating method includes generating third information including first information and second information, wherein the first information indicates whether updating of regions of a register block is allowed and the second information includes information that is to be updated in the register block, transmitting the third information to an address of the register block that is to be updated, and selecting a part of the second information in a unit of the regions and writing the selected second information to the register block, based on the first information included in the received third information.

Abstract: A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address signal, and a write permission signal. The storage unit writes and stores input data, in response to the first control signal. The write permission signal is received from an external source and indicates whether to protect the written data.

Abstract: Provided are a digital signal processor controlled according to handshake interfacing and a method of operating the digital signal processor. The method of operating the digital signal processor may comprise receiving a request signal for executing an application program from an external device, reading an address corresponding to the request signal, reading an application program code corresponding to the address from a program memory storing at least one application program code and executing the requested application program according to the read application program code, and outputting an acknowledge signal representing the completion of the execution of the application program to the external device when the execution of the application program has ended.