Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.

Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.

Abstract: A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.

Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.

Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.

Abstract: A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties.

Abstract: A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties.

Abstract: A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell.

Abstract: There is provided a semiconductor memory device having a multibank in which a single large memory cell is divided into a plurality of banks without increasing power consumption and chip size. In the semiconductor memory device, a memory cell array is divided into a plurality of banks arranged alternately, and each bank includes a plurality of unit memory cell arrays. In addition, column selection lines of each bank are connected to alternate output ports of a column decoder, and the column decoder enables the column selection lines of a bank selected from the plurality of banks in response to address decoding signals and bank selection signals.

Abstract: A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off.

Abstract: There is disclosed a semiconductor memory device that has a memory-cell array with memory cells arranged in a matrix, bit-line sense amplifiers connected to bit lines of the memory-cell array, a row address predecoder performing decoding of some of row address signals in response to a system clock, and a plurality of banks having an output line of the row address predecoder in common, includes: a row strobe buffer connected to an external system and producing a first control signal for selecting corresponding banks in response to the system clock, a row address strobe signal, and a bank selection address signal and for controlling generation of a row address sampling control signal; a row address sampling control signal generating circuit producing the row address sampling control signal in a predetermined period of time in response to generation of the first control signal produced by the row strobe buffer in order to control word-line activating and precharging operations; and a row decoder latching an outp

Abstract: A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled.

Abstract: There is disclosed a semiconductor memory device that has a memory-cell array with memory cells arranged in a matrix, bit-line sense amplifiers connected to bit lines of the memory-cell array, a row address predecoder performing decoding of some of row address signals in response to a system clock, and a plurality of banks having an output line of the row address predecoder in common, includes: a row strobe buffer connected to an external system and producing a first control signal for selecting corresponding banks in response to the system clock, a row address strobe signal, and a bank selection address signal and for controlling generation of a row address sampling control signal; a row address sampling control signal generating circuit producing the row address sampling control signal in a predetermined period of time in response to generation of the first control signal produced by the row strobe buffer in order to control word-line activating and precharging operations; and a row decoder latching an outp