Patents by Inventor Moon-Han Park

Moon-Han Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733304
    Abstract: A user device may strengthen the protection level of a digital content by dividing the security and normal modes and performing an operation. In order to further strengthen the protection level of the digital content, the user device may determine whether the main operating system is hacked or not, and blocks the operation in the secure mode. Otherwise, the device authorization information indicating the device security level of the user device is authorized by the content service server, and the user device blocks the operation in the secure mode according to the result.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Soo Chang, Seul-Han Park, Yang-Soo Lee
  • Publication number: 20200243398
    Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gun Ho JO, Dae Joung KIM, Jae Mun KIM, Moon Han PARK, Tae Ho CHA, Jae Jong HAN
  • Patent number: 10658249
    Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gun Ho Jo, Dae Joung Kim, Jae Mun Kim, Moon Han Park, Tae Ho Cha, Jae Jong Han
  • Patent number: 10379395
    Abstract: A color conversion panel includes a substrate, a light blocking layer on the substrate, and color conversion layers and a transmission layer on the substrate, the color conversion layers including a quantum dot, wherein the light blocking layer includes a first sub-light blocking layer overlapping the color conversion layers and the transmission layer, and a second sub-light blocking layer between adjacent ones of the color conversion layers and the transmission layer, and wherein each of the first sub-light blocking layer and the second sub-light blocking layer includes an external light absorption layer on the substrate, and a reflection layer on the external light absorption layer.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang Keun Lee, Young Min Kim, Hae Il Park, Moon Jung Baek, Seon-Tae Yoon, Jun Han Lee
  • Publication number: 20190218642
    Abstract: Disclosed is a thermal reduction apparatus. The thermal reduction apparatus according to the exemplary embodiment includes: a preheating unit which preheats a to-be-reduced material and loads the to-be-reduced material into a reducing unit; the reducing unit which is connected to the preheating unit and in which a thermal reduction reaction of the to-be-reduced material occurs; a cooling unit which is connected to the reducing unit and from which the to-be-reduced material flowing into the cooling unit is unloaded to the outside; a gate device which is installed between the preheating unit and the reducing unit; a gate device which is installed between the reducing unit and the cooling unit; a condensing device which is connected to the reducing unit and condenses a metal vapor; a first blocking unit which is installed in the reducing unit; and a second blocking unit which is installed in the reducing unit so as to be spaced apart from the first blocking unit.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Inventors: Dong Kyun CHOO, Young II KIM, Kil Won CHO, Wung Yong CHOO, Jong Min PARK, Jae Sin PARK, Gilsoo HAN, Good-Sun CHOI, Gyu Chang LEE, Dae Kyu PARK, Moon Chui KIM
  • Publication number: 20190148521
    Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 16, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gun Ho JO, Dae Joung KIM, Jae Mun KIM, Moon Han PARK, Tae Ho CHA, Jae Jong HAN
  • Patent number: 10287651
    Abstract: Disclosed is a thermal reduction apparatus. The thermal reduction apparatus according to the exemplary embodiment includes: a preheating unit which preheats a to-be-reduced material and loads the to-be-reduced material into a reducing unit; the reducing unit which is connected to the preheating unit and in which a thermal reduction reaction of the to-be-reduced material occurs; a cooling unit which is connected to the reducing unit and from which the to-be-reduced material flowing into the cooling unit is unloaded to the outside; a gate device which is installed between the preheating unit and the reducing unit; a gate device which is installed between the reducing unit and the cooling unit; a condensing device which is connected to the reducing unit and condenses a metal vapor; a first blocking unit which is installed in the reducing unit; and a second blocking unit which is installed in the reducing unit so as to be spaced apart from the first blocking unit.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 14, 2019
    Assignee: RESEARCH INSTITUTE OF INDUSTRIAL SCIENCE & TECHNOLOGY
    Inventors: Dong Kyun Choo, Young Il Kim, Kil Won Cho, Wung Yong Choo, Jong Min Park, Jae Sin Park, Gilsoo Han, Good-Sun Choi, Gyu Chang Lee, Dae Kyu Park, Moon Chul Kim
  • Publication number: 20190139771
    Abstract: To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.
    Type: Application
    Filed: July 17, 2018
    Publication date: May 9, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-woo Kang, Ji-ho Yoo, Dong-hoon Khang, Seon-bae Kim, Moon-han Park
  • Patent number: 10224204
    Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoon Khang, Dong-Woo Kang, Moon-Han Park, Ji-Ho Yoo, Chong-Kwang Chang
  • Publication number: 20190051526
    Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.
    Type: Application
    Filed: February 8, 2018
    Publication date: February 14, 2019
    Inventors: DONG-HOON KHANG, DONG-WOO KANG, MOON-HAN PARK, JI-HO YOO, CHONG-KWANG CHANG
  • Patent number: 9793399
    Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pan-Kwi Park, Koung-Min Ryu, Moon-Han Park, Hyung-suk Jung, Jong-hoon Baek, Su-Young Choi
  • Publication number: 20160020324
    Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.
    Type: Application
    Filed: December 17, 2014
    Publication date: January 21, 2016
    Inventors: Pan-Kwi Park, Koung-Min Ryu, Moon-Han Park, Hyung-suk Jung, Jong-hoon Baek, Su-Young Choi
  • Patent number: 8877579
    Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-kyun Song, Ha-jin Lim, Moon-han Park, Jin-ho Do
  • Patent number: 8815673
    Abstract: In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-ho Do, Moon-han Park, Weon-hong Kim, Kyung-il Hong
  • Patent number: 8664111
    Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Ha-Jin Lim, Moon-Han Park, Eun-Gon Kim, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
  • Patent number: 8455345
    Abstract: A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Moon-Han Park, Min-Woo Song, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
  • Publication number: 20120309144
    Abstract: In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: December 6, 2012
    Inventors: Jin-ho Do, Moon-han Park, Weon-hong Kim, Kyung-il Hong
  • Publication number: 20120309145
    Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.
    Type: Application
    Filed: March 12, 2012
    Publication date: December 6, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon-kyun Song, Ha-jin Lim, Moon-han Park, Jin-ho Do
  • Publication number: 20120083111
    Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 5, 2012
    Inventors: Ha-Jin Lim, Moon-Han Park, Eun-Gon Kim, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
  • Publication number: 20120070975
    Abstract: A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 22, 2012
    Inventors: Ha-Jin Lim, Moon-Han Park, Min-Woo Song, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo