Patents by Inventor Moon J. Chung

Moon J. Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020087038
    Abstract: The present invention relates to a process for preparing hexafluoropropylene(CF3CF=CF2, HFP) from the pyrolysis of trifluoromethane(CHF3, R23) and tetrafluoroethylene(C2F4, TFE) and more particularly, to the process for preparing hexafluoropropylene from the pyrolysis of an admixture of R23 and TFE mixed in an appropriate molar ratio at below 900 which is lower than the conventional reaction temperature and longer residence time, after investigating the pyrolysis reaction of R23 and TFE by the computer simulation. The process for preparing HFP is performed by carefully controlling reaction temperature with heat balance resulted from an endothermic pyrolysis of R23 and an exothermic dimerization of TFE to prevent from carbon formation, recycling unreacted R23 and TFE in the product separated and purified from distillation column, adding fresh R23 additionally to keep an appropriate molar ratio of R23 and TFE, to improve a total yield of HFP and to minimize heat supply from outside.
    Type: Application
    Filed: March 30, 2001
    Publication date: July 4, 2002
    Inventors: Dong J. Moon, Hong G. Kim, Byoung S. Ahn, Moon J. Chung, Young S. Kwon
  • Patent number: 5745500
    Abstract: A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: April 28, 1998
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Thyagaraju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael