Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: A performance-adjustable memory module configured for power consumption optimization is provided. In a typical approach, the memory module (e.g., a DRAM-type memory module) comprises a set of memory segments coupled to a set of power supplies. A controller (e.g., an external controller) will supply control information via a set of control registers that is used to vary levels of power provided by the set of power supplies to the set of memory segments. The varying levels of power allow for the performance levels of the set of memory segment to be varied, and thus provide a more optimized memory system.

Abstract: The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc.

Abstract: An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

Abstract: Embodiments of the present invention provide an adaptive and intelligent fingerprint scanning device and approach. Specifically, embodiments of the present invention utilize DC resistive image scanning to reduce overall scanning time and energy consumption (e.g., by identifying a targeted scanning area). In a typical embodiment, a scanning device will be provided that includes a scanning area comprised of a set (e.g., at least one) of imaging pixel electrodes (e.g., arranged adjacent to one another in a grid-like or other fashion). As a user presses his/her finger against the scanning area, a first portion of the finger will contact a first electrode while a second portion of the finger will contact a second electrode. When this occurs, a voltage source of the device will apply an initial voltage across the first and second finger portions. A meter of the device will take an electrical measurement (e.g., resistance and/or charged skin voltage) across the two finger portions.

Abstract: In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc.

Abstract: In general, embodiments of the present invention relate to a light-powered smart card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises (among other things) an energy component for providing power to the card. Upon powering up via a light source, including light from the interfacing terminal's backlight, a terminal (e.g., a point of sale terminal) will scan/read card information shared between the card and the card company (e.g., upon swiping or placing of the card), and generate a corresponding source validation code (SVC). An optional imager/image array positioned on the back of the card will scan/read the SVC, and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC).

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.

Abstract: Embodiments of the present invention provide an adaptive and intelligent fingerprint scanning device and approach for a multi-sided card. Specifically, embodiments of the present invention utilize DC resistive image scanning to reduce overall scanning time and energy consumption (e.g., by identifying a targeted scanning area). In a typical embodiment, a scanning device will be provided that includes a scanning area comprised of a set (e.g., at least one) of imaging pixel electrodes (e.g., arranged adjacent to one another in a grid-like or other fashion). As a user presses his/her finger against the scanning area, a first portion of the finger will contact a first electrode while a second portion of the finger will contact a second electrode. When this occurs, a voltage source of the device will apply an initial voltage across the first and second finger portions. A meter of the device will take an electrical measurement (e.g., resistance and/or charged skin voltage) across the two finger portions.

Abstract: Embodiments of the present invention provide various approaches for mobile device intercommunication (e.g., digital) as well as various authentication methods. In one embodiment, the present invention provides direct line-of-sight visual digital communication between mobile devices for controlled security. In another embodiment, the present invention provides direct contact motion-based digital communication between mobile devices for controlled security. Embodiments of the present invention also provide various authentication methods. One such example relates to secure authentication code exchange with subsequent digital communications in one or more channels. In another example, human-readable information is used along machine-readable digital codes (e.g., quick response (QR) codes to verify visual codes. Still yet, embodiments of the present invention provide non-obtrusive visual codes that maintain a user's access to a mobile device screen.

Abstract: Embodiments of the present invention provide a semiconductor storage device (SSD) system based on asymmetric RAID storage. Specifically, embodiments of this invention provide a set of (at least one) of RAID controllers coupled to a host computer. A set of storage drives is coupled to each asymmetric RAID controller. The RAID method and configuration of each storage device are dynamically adapted based on user policy parameters and storage performance characteristics.

Abstract: Embodiments of the present invention provide a memory configuration on a chip containing multiple memory segments having different memory grades. In a typical embodiment, a single chip will be provided on which the memory segments are positioned. A memory grade may include low performance (low leakage), medium performance (medium leakage), and high performance (high leakage). Each memory segment or group of memory segments may have a separate power supply and/or controller. In one example, memory segments may be stacked in a through-silicon via configuration.

Abstract: In general, embodiments of the present invention relate to a card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises an energy component for providing power to the card and a back display (e.g., positioned on the back or magnetic strip side of the card) for displaying card information being used in the commercial transaction. Upon display, a terminal (e.g., a point of sale terminal) will scan/read the card information and generate a corresponding source validation code (SVC). An imager positioned on the back of the card will scan/read the SVC and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC).

Abstract: Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

Abstract: The present invention relates to a server-processor hybrid system that comprises (among other things) a set (one or more) of front-end servers (e.g., mainframes) and a set of back-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor.

Abstract: Embodiments of the present invention provide various approaches for mobile device intercommunication (e.g., digital) as well as various authentication methods. In one embodiment, the present invention provides direct line-of-sight visual digital communication between mobile devices for controlled security. In another embodiment, the present invention provides direct contact motion-based digital communication between mobile devices for controlled security. Embodiments of the present invention also provide various authentication methods. One such example relates to secure authentication code exchange with subsequent digital communications in one or more channels. In another example, human-readable information is used along machine-readable digital codes (e.g., quick response (QR) codes to verify visual codes. Still yet, embodiments of the present invention provide non-obtrusive visual codes that maintain a user's access to a mobile device screen.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: The present invention relates to a server-processor hybrid system that comprises (among other things) a set (one or more) of front-end servers (e.g., mainframes) and a set of back-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor.