Abstract: A light-emitting element, a method of fabricating a light-emitting element, and a display device comprising a light-emitting element are provided. The light-emitting element comprises a first semiconductor layer doped with an n-type dopant, a second semiconductor layer doped with a p-type dopant, a light-emitting layer disposed between the first semiconductor layer and second semiconductor layer, an electrode layer disposed on the second semiconductor layer, an insulating structure disposed on the electrode layer and having a maximum diameter smaller than a diameter of the electrode layer and an insulating film that surrounds side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer.

Abstract: The present invention relates to a method of preparing a graft polymer, which includes: preparing a second diene-based rubber polymer by enlarging a first diene-based rubber polymer with an acidic group-containing acrylic polymer; preparing a first mixture comprising the second diene-based rubber polymer and a non-ionic emulsifier; and preparing a graft polymer latex by polymerizing an aromatic vinyl-based monomer and a vinyl cyanide-based monomer in the presence of the first mixture.

Abstract: Disclosed is a substrate processing apparatus including: a support unit for supporting a substrate and rotating the substrate; a solution discharge unit for discharging a processing solution including a first material and a second material onto the substrate to remove a film on the substrate; and a controller for controlling the solution discharge unit, in which the controller sets, when the solution discharge unit discharges the processing solution to a first position and a second position on the substrate, a hydrogen ion concentration of the processing solution discharged to the first position to be different from a hydrogen ion concentration of the processing solution discharged to the second position, and the first position is a center of the substrate or is located closer to the center of the substrate than the second position.

Abstract: A muscular strength assisting apparatus includes a muscular strength assisting portion that assists a user's muscular strength and a first connecting link including one side connected to one side of the muscular strength assisting portion and an opposite side rotatable relative to a shoulder of the user about a first rotation axis. The muscular strength assisting portion includes an upper arm module that assists muscular strength of an upper arm of the user and a link assembly including one side connected to one side of the upper arm module to be rotatable about a second rotation axis non-parallel to the first rotation axis and an opposite side disposed adjacent to a portion of a body of the user to be supported on the user.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

Abstract: An electronic device may contain clock circuits, transmitters, and other circuits that serve as sources of noise signals. The noise signals may be characterized by a noise spectrum. The noise spectrum produced by a noise source can be adjusted by adjusting spread spectrum clock circuitry in a clock circuit, by adjusting data scrambling circuitry in a transmitter circuit, or by making other dynamic adjustments to the circuitry of the electronic device. During operation of the electronic device, sensitive circuitry in the device such as wireless receiver circuitry may be adversely affected by the presence of noise from a noise source in the device. Based on information such as which receiver bands and/or channels are being actively received and target sensitivity levels for the receiver circuitry, control circuitry within the electronic device can determine in real time how to minimize interference between the noise source and the wireless receiver circuitry.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract: The antenna on hand held devices, such as the iPhone or iPad, can be subject to interference from other circuitry on the device. Such interference may come from high frequency switching of nearby display circuitry, such as de-multiplexors or other circuits. To address this issue, the switching rates may be slowed in certain circuits by adding resistance and/or capacitance, thus raising the RC time constant and slowing the switching times to reduce the high frequency components. Alternatively or in addition to, an EMI shield can be placed over some or all of the display driving circuitry to shield the antenna from high frequency interference.

Abstract: An electronic device may contain clock circuits, transmitters, and other circuits that serve as sources of noise signals. The noise signals may be characterized by a noise spectrum. The noise spectrum produced by a noise source can be adjusted by adjusting spread spectrum clock circuitry in a clock circuit, by adjusting data scrambling circuitry in a transmitter circuit, or by making other dynamic adjustments to the circuitry of the electronic device. During operation of the electronic device, sensitive circuitry in the device such as wireless receiver circuitry may be adversely affected by the presence of noise from a noise source in the device. Based on information such as which receiver bands and/or channels are being actively received and target sensitivity levels for the receiver circuitry, control circuitry within the electronic device can determine in real time how to minimize interference between the noise source and the wireless receiver circuitry.

Abstract: The antenna on hand held devices, such as the iPhone or iPad, can be subject to interference from other circuitry on the device. Such interference may come from high frequency switching of nearby display circuitry, such as de-multiplexors or other circuits. To address this issue, the switching rates may be slowed in certain circuits by adding resistance and/or capacitance, thus raising the RC time constant and slowing the switching times to reduce the high frequency components. Alternatively or in addition to, an EMI shield can be placed over some or all of the display driving circuitry to shield the antenna from high frequency interference.

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract: A semiconductor device, a method related to the semiconductor device, and a printed circuit board are disclosed. The semiconductor device includes a chip, a package including a plurality of power voltage terminals and a plurality of ground voltage terminals, wherein the chip is disposed in the package. The semiconductor device further includes an impedance circuit connected between a DC component power voltage terminal and a ground voltage, wherein the DC component power voltage terminal is one of the plurality of power voltage terminals, and an AC component interrupter connected between the DC component power voltage terminal and a power voltage. Both the AC component and a DC component of the power voltage are applied to each of the power voltage terminals except the DC component second power voltage terminal, and the ground voltage is applied to each of the ground voltage terminals.

Abstract: An inline memory module (IMM) architecture may include: a printed circuit board (PCB); a first array of memory devices on a first side of the PCB; a second array of memory devices on a second side of the PCB; at least some of the memory devices of the first array being arranged so as to substantially overlap, relative to a reference axis of the PCB, positional-twin memory devices of the second array, respectively; and multiple vias at least some of which are parts of respective signal paths that connect signal leads of a first memory device in the first array to corresponding signal leads of a second memory device in the second array that is adjacent to a positional-twin third memory device in the second array corresponding to the first memory device.

Abstract: A semiconductor device, a method related to the semiconductor device, and a printed circuit board are disclosed. The semiconductor device includes a chip, a package including a plurality of power voltage terminals and a plurality of ground voltage terminals, wherein the chip is disposed in the package. The semiconductor device further includes an impedance circuit connected between a DC component power voltage terminal and a ground voltage, wherein the DC component power voltage terminal is one of the plurality of power voltage terminals, and an AC component interrupter connected between the DC component power voltage terminal and a power voltage. Both the AC component and a DC component of the power voltage are applied to each of the power voltage terminals except the DC component second power voltage terminal, and the ground voltage is applied to each of the ground voltage terminals.

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract: A semiconductor module may include a printed circuit board that may have a first surface, a second surface, and at least one fixture hole. A semiconductor device may be mounted on the first surface of the printed circuit board. At least one connection terminal may be provided on one of the first surface or the second surface of the printed circuit board that may connect with connection pads of a motherboard. The printed circuit board may be connected to the motherboard through the at least one fixture hole such the connection terminals may be aligned with the connection pad and one of the first surface and second surface of the printed circuit board may face a major surface of the motherboard.

Abstract: A multilayered circuit substrate and a semiconductor package using the multilayered circuit substrate are provided to increase the number of bonding pads arranged on the circuit substrate without reducing the pitch of the bonding pads, and to further increase the routing feasibility of high speed signals by the use of signal wirings instead of vias. An embodiment may include bonding pads provided on different layers, in which the bonding pads arranged on one layer are staggered with the bonding pad arranged on another layer. Ball lands may be connected to the bonding pads using wirings wherein the bonding pads connected to the signal wirings may be provided on the same layer as the corresponding ball lands.

Abstract: An inline memory module (IMM) architecture may include: a printed circuit board (PCB); a first array of memory devices on a first side of the PCB; a second array of memory devices on a second side of the PCB; at least some of the memory devices of the first array being arranged so as to substantially overlap, relative to a reference axis of the PCB, positional-twin memory devices of the second array, respectively; and multiple vias at least some of which are parts of respective signal paths that connect signal leads of a first memory device in the first array to corresponding signal leads of a second memory device in the second array that is adjacent to a positional-twin third memory device in the second array corresponding to the first memory device.