Patents by Inventor Moon-seung Yang
Moon-seung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942551Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.Type: GrantFiled: November 5, 2021Date of Patent: March 26, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Taek Kim, Seok Hoon Kim, Pan Kwi Park, Moon Seung Yang, Seo Jin Jeong, Min-Hee Choi, Ryong Ha
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Publication number: 20230402510Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and a source/drain pattern on a side surface of the channel pattern, the source/drain pattern including a first section between a first level and a second level that is higher than the first level, a first variation section between the second level and a third level that is higher than the second level, and a second section between the third level and a fourth level that is higher than the third level, where a rate of change in germanium concentration in the first variation section in a first direction is greater than a rate of change in germanium concentration in each of the first section and the second section in the first direction, and a germanium concentration at each of the first level and the second level is greater than 0 at % and equal to or less than 10 at %.Type: ApplicationFiled: January 24, 2023Publication date: December 14, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Namkyu CHO, Jungtaek Kim, Moon Seung Yang, Sumin Yu, Seojin Jeong, Seokhoon Kim, Pankwi Park
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Patent number: 11710772Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.Type: GrantFiled: December 23, 2021Date of Patent: July 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eunhye Choi, Seung Mo Kang, Jungtaek Kim, Moon Seung Yang, Jongryeol Yoo
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Patent number: 11688813Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.Type: GrantFiled: January 26, 2022Date of Patent: June 27, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Mo Kang, Moon Seung Yang, Jongryeol Yoo, Sihyung Lee, Sunguk Jang, Eunhye Choi
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Publication number: 20230111579Abstract: A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.Type: ApplicationFiled: July 26, 2022Publication date: April 13, 2023Inventors: RYONG HA, SEOKHOON KIM, DOHYUN GO, JUNGTAEK KIM, MOON SEUNG YANG, SANGIL LEE, SEOJIN JEONG
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Patent number: 11569389Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: GrantFiled: September 9, 2021Date of Patent: January 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Seung Yang, Eun Hye Choi, Seung Mo Kang, Yong Seung Kim, Jung Taek Kim, Min-Hee Choi
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Publication number: 20220190168Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.Type: ApplicationFiled: November 5, 2021Publication date: June 16, 2022Inventors: Jung Taek Kim, Seok Hoon Kim, Pan Kwi Park, Moon Seung Yang, Seo Jin Jeong, Min-Hee Choi, Ryong Ha
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Publication number: 20220190134Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.Type: ApplicationFiled: August 30, 2021Publication date: June 16, 2022Inventors: SEO JIN JEONG, Do Hyun GO, Seok Hoon KIM, Jung Taek KIM, Pan Kwi PARK, Moon Seung YANG, Min-Hee CHOI, Ryong HA
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Publication number: 20220181500Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.Type: ApplicationFiled: November 23, 2021Publication date: June 9, 2022Inventors: Ryong Ha, Seok Hoon Kim, Jung Taek Kim, Pan Kwi Park, Moon Seung Yang, Seo Jin Jeong
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Publication number: 20220149210Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Seung Mo KANG, Moon Seung YANG, Jongryeol YOO, Sihyung LEE, Sunguk JANG, Eunhye CHOI
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Publication number: 20220115500Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Inventors: Eunhye CHOI, Seung Mo KANG, Jungtaek KIM, Moon Seung YANG, Jongryeol YOO
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Patent number: 11251313Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.Type: GrantFiled: January 28, 2020Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Mo Kang, Moon Seung Yang, Jongryeol Yoo, Sihyung Lee, Sunguk Jang, Eunhye Choi
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Publication number: 20210408300Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: ApplicationFiled: September 9, 2021Publication date: December 30, 2021Inventors: Moon Seung YANG, Eun Hye CHOI, Seung Mo KANG, Yong Seung KIM, Jung Taek KIM, Min-Hee CHOI
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Patent number: 11211457Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.Type: GrantFiled: June 12, 2020Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eunhye Choi, Seung Mo Kang, Jungtaek Kim, Moon Seung Yang, Jongryeol Yoo
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Patent number: 11133421Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: GrantFiled: March 4, 2020Date of Patent: September 28, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Seung Yang, Eun Hye Choi, Seung Mo Kang, Yong Seung Kim, Jung Taek Kim, Min-Hee Choi
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Publication number: 20200395445Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.Type: ApplicationFiled: June 12, 2020Publication date: December 17, 2020Inventors: Eunhye CHOI, Seung Mo KANG, Jungtaek KIM, Moon Seung YANG, Jongryeol YOO
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Publication number: 20200395489Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.Type: ApplicationFiled: March 4, 2020Publication date: December 17, 2020Inventors: Moon Seung YANG, Eun Hye CHOI, Seung Mo KANG, Yong Seung KIM, Jung Taek KIM, Min-Hee CHOI
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Publication number: 20200381564Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.Type: ApplicationFiled: January 28, 2020Publication date: December 3, 2020Inventors: Seung Mo KANG, Moon Seung YANG, Jongryeol YOO, Sihyung LEE, Sunguk JANG, Eunhye CHOI
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Patent number: 10008575Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.Type: GrantFiled: October 20, 2016Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Chan Suh, Yong Suk Tak, Gi Gwan Park, Mi Seon Park, Moon Seung Yang, Seung Hun Lee, Poren Tang
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Patent number: 9929239Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.Type: GrantFiled: February 23, 2016Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-soo Lee, Myoung-jae Lee, Seong-ho Cho, Mohammad Rakib Uddin, David Seo, Moon-seung Yang, Sang-moon Lee, Sung-hun Lee, Ji-hyun Hur, Eui-chul Hwang