Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The memory cells may be coupled to a plurality of word lines. The peripheral circuit may perform a memory operation on selected memory cells. The control logic may control the peripheral circuit, during the memory operation, to apply an operating voltage to a selected word line, among the plurality of word lines, coupled to the selected memory cells, a first pass voltage to target word lines adjacent to the selected word line among unselected word lines, based on whether the operating voltage is lower than or equal to a reference voltage, and a second pass voltage, having a lower level than the first pass voltage, to remaining unselected word lines, other than the target word lines.

Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.

Abstract: Disclosed is an operating method of a controller for controlling an operation of a semiconductor memory device including a plurality of memory cells. In the operating method of the controller, program data to be stored in a selected page of the semiconductor memory device is generated, and the semiconductor memory device is controlled to program the program data in the selected page. Bit data at a predetermined position in the program data is data for allowing a threshold voltage of a corresponding memory cell to maintain an erase state.

Abstract: A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.

Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.

Abstract: A method of manufacturing a three-dimensional semiconductor memory device includes forming a preliminary channel hole through a vertical stack structure including first layers and second layers that are alternately stacked, oxidizing an inner surface of the preliminary channel hole to form a sacrificial layer, removing the sacrificial layer to form a final channel hole, and forming a channel plug in the final channel hole.

Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.

Abstract: A memory device, and methods of manufacturing and operating the memory device, include alternately stacked interlayer insulating layers and conductive layers, a vertical hole configured to pass through the alternately stacked conductive layers and interlayer insulating layers, first blocking layers formed along the interlayer insulating layers exposed through the vertical hole, and second blocking layers formed along the conductive layers exposed through the vertical hole, with each second blocking layer having a thickness greater than that of each of the first blocking layers. The memory device also includes charge trap layers formed on the same layer as the interlayer insulating layers, and surrounded by the first and second blocking layers, a tunnel insulating layer formed along inner walls of the second blocking layers and the charge trap layers, and a channel layer formed along an inner wall of the tunnel insulating layer.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The memory cells may be coupled to a plurality of word lines. The peripheral circuit may perform a memory operation on selected memory cells. The control logic may control the peripheral circuit, during the memory operation, to apply an operating voltage to a selected word line, among the plurality of word lines, coupled to the selected memory cells, a first pass voltage to target word lines adjacent to the selected word line among unselected word lines, based on whether the operating voltage is lower than or equal to a reference voltage, and a second pass voltage, having a lower level than the first pass voltage, to remaining unselected word lines, other than the target word lines.

Abstract: Disclosed is an operating method of a controller for controlling an operation of a semiconductor memory device including a plurality of memory cells. In the operating method of the controller, program data to be stored in a selected page of the semiconductor memory device is generated, and the semiconductor memory device is controlled to program the program data in the selected page. Bit data at a predetermined position in the program data is data for allowing a threshold voltage of a corresponding memory cell to maintain an erase state.

Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.

Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.

Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.

Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.

Abstract: A memory device, and a method of operating the memory device, includes: a memory cell array including a plurality of strings; a voltage generation circuit configured to apply a turn-on voltage to the plurality of strings during a set application period in a channel initialization operation of a read operation of a selected string among the plurality of strings; a temperature detection circuit configured to measure an internal temperature of the memory device and generate a temperature signal; and control logic configured to control the voltage generation circuit to set the application period in response to the temperature signal and apply the turn-on voltage to the plurality of strings during the set application period.

Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.

Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.

Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.

Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.