Patents by Inventor Moon Sik SEO

Moon Sik SEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217456
    Abstract: A memory device, and a method of operating the memory device, includes: a memory cell array including a plurality of strings; a voltage generation circuit configured to apply a turn-on voltage to the plurality of strings during a set application period in a channel initialization operation of a read operation of a selected string among the plurality of strings; a temperature detection circuit configured to measure an internal temperature of the memory device and generate a temperature signal; and control logic configured to control the voltage generation circuit to set the application period in response to the temperature signal and apply the turn-on voltage to the plurality of strings during the set application period.
    Type: Application
    Filed: July 7, 2020
    Publication date: July 15, 2021
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Moon Sik SEO
  • Patent number: 11062783
    Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Moon Sik Seo
  • Patent number: 11031086
    Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Moon Sik Seo
  • Publication number: 20210104281
    Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.
    Type: Application
    Filed: May 5, 2020
    Publication date: April 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Moon Sik SEO
  • Publication number: 20210027848
    Abstract: A memory device includes a memory cell array having a plurality of memory strings and includes a voltage generating circuit configured to generate and apply a plurality of drain select line voltages, a plurality of source select line voltages, and a read voltage to the memory cell array during a read operation. The memory device also includes control logic configured to control the voltage generating circuit to generate a first drain select line voltage applied to a first unselected memory string among unselected memory strings among the plurality of memory strings and a second drain select line voltage applied to second unselected memory strings among the unselected memory strings during the read operation, wherein the second drain select line voltage is different from the first drain select line voltage.
    Type: Application
    Filed: October 18, 2019
    Publication date: January 28, 2021
    Applicant: SK hynix Inc.
    Inventor: Moon Sik SEO
  • Publication number: 20200395372
    Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.
    Type: Application
    Filed: October 23, 2019
    Publication date: December 17, 2020
    Inventors: Moon Sik SEO, Gil Bok CHOI
  • Patent number: 9558827
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 31, 2017
    Assignee: SK Hynix Inc.
    Inventors: Moon Sik Seo, Kyung Sik Mun
  • Patent number: 9530848
    Abstract: Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventor: Moon Sik Seo
  • Publication number: 20160172048
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.
    Type: Application
    Filed: April 27, 2015
    Publication date: June 16, 2016
    Inventors: Moon Sik SEO, Kyung Sik MUN
  • Publication number: 20160163394
    Abstract: A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Hyun Seung YOO, Moon Sik SEO
  • Patent number: 9299714
    Abstract: A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 29, 2016
    Assignees: SK HYNIX INC., TOHOKU UNIVERSITY
    Inventors: Moon-Sik Seo, Tetsuo Endoh
  • Patent number: 9293208
    Abstract: A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyun Seung Yoo, Moon Sik Seo
  • Publication number: 20150303269
    Abstract: Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 22, 2015
    Inventor: Moon Sik SEO
  • Patent number: 9105513
    Abstract: Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: August 11, 2015
    Assignee: SK Hynix Inc.
    Inventor: Moon Sik Seo
  • Publication number: 20150194437
    Abstract: A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.
    Type: Application
    Filed: March 18, 2015
    Publication date: July 9, 2015
    Inventors: Moon-Sik SEO, Tetsuo ENDOH
  • Publication number: 20150123182
    Abstract: Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern.
    Type: Application
    Filed: April 10, 2014
    Publication date: May 7, 2015
    Applicant: SK HYNIX INC.
    Inventor: Moon Sik SEO
  • Patent number: 9012971
    Abstract: A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 21, 2015
    Assignees: SK Hynix Inc., Tohoku University
    Inventors: Moon Sik Seo, Tetsuo Endoh
  • Publication number: 20150085576
    Abstract: A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.
    Type: Application
    Filed: February 25, 2014
    Publication date: March 26, 2015
    Applicant: SK hynix Inc.
    Inventors: Hyun Seung YOO, Moon Sik SEO
  • Publication number: 20140131785
    Abstract: A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.
    Type: Application
    Filed: December 13, 2012
    Publication date: May 15, 2014
    Applicants: TOHOKU UNIVERSITY, SK HYNIX INC.
    Inventors: Moon Sik SEO, Tetsuo ENDOH