Patents by Inventor Moon Sik Suh
Moon Sik Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7723768Abstract: Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on a semiconductor substrate by gap-filling the recess regions, and misaligned with the recess region corresponding to one of the source/drain regions; spacers formed on sides of the recessed gate electrodes; and source/drain regions implanted with a dopant formed in the semiconductor substrate exposed between the spacers. The overlap between the gate electrodes and the source/drain regions can be reduced by having one of the source/drain regions misaligned with the recess regions in the recessed gate structure, and abnormal leakage current caused by consistency between an electron field max point A and a stress max pint B can be sharply reduced by changing the profile of the source/drain regions.Type: GrantFiled: May 16, 2005Date of Patent: May 25, 2010Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Patent number: 7622353Abstract: Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of a resultant device, and a method for forming the same. The recess-gate structure comprises a silicon substrate in which an active region and a device isolation region are defined, a plurality of gates formed on the substrate, gate spacers formed at the side wall of the respective gates, and junctions formed in the substrate at opposite lateral sides of the gates and defining an asymmetrical structure relative to each other. A gate recess is defined in the active region of the substrate to have a stepped profile consisting of a bottom plane, top plane, and vertical plane.Type: GrantFiled: August 8, 2008Date of Patent: November 24, 2009Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Patent number: 7518198Abstract: A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain junctions having asymmetrical junction structures, respectively, wherein the gate has a lower portion arranged on the active region of the substrate, the lower gate portion having a stepped profile having a lower surface, an upper surface and a vertically-extending side surface. The invention also provides a method for manufacturing this transistor. In accordance with this transistor structure, an increase in the dopant concentration of a storage node is prevented. Accordingly, a reduction in the amount of leakage current is achieved, so that an improvement in the refresh characteristics of the transistor is achieved.Type: GrantFiled: June 7, 2007Date of Patent: April 14, 2009Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Publication number: 20090004798Abstract: Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of a resultant device, and a method for forming the same. The recess-gate structure comprises a silicon substrate in which an active region and a device isolation region are defined, a plurality of gates formed on the substrate, gate spacers formed at the side wall of the respective gates, and junctions formed in the substrate at opposite lateral sides of the gates and defining an asymmetrical structure relative to each other. A gate recess is defined in the active region of the substrate to have a stepped profile consisting of a bottom plane, top plane, and vertical plane.Type: ApplicationFiled: August 8, 2008Publication date: January 1, 2009Applicant: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Patent number: 7423318Abstract: Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of a resultant device, and a method for forming the same. The recess-gate structure comprises a silicon substrate in which an active region and a device isolation region are defined, a plurality of gates formed on the substrate, gate spacers formed at the side wall of the respective gates, and junctions formed in the substrate at opposite lateral sides of the gates and defining an asymmetrical structure relative to each other. A gate recess is defined in the active region of the substrate to have a stepped profile consisting of a bottom plane, top plane, and vertical plane.Type: GrantFiled: June 14, 2005Date of Patent: September 9, 2008Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Patent number: 7381612Abstract: Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substrate, which includes storage nodes junction, the bit line junction, and channel regions between the source and bit line junctions, and portions of the channel regions of the semiconductor substrate adjacent to the bit line junction; forming recess channel trenches by etching the channel regions of the semiconductor substrate to a designated depth; forming a gate stack on the semiconductor substrate provided with the recess channel trenches; and forming the storage nodes junction and the bit line junction on the semiconductor substrate provided with the gate stack via ion implantation.Type: GrantFiled: June 24, 2005Date of Patent: June 3, 2008Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Patent number: 7244650Abstract: A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain junctions having asymmetrical junction structures, respectively, wherein the gate has a lower portion arranged on the active region of the substrate, the lower gate portion having a stepped profile having a lower surface, an upper surface and a vertically-extending side surface. The invention also provides a method for manufacturing this transistor. In accordance with this transistor structure, an increase in the dopant concentration of a storage node is prevented. Accordingly, a reduction in the amount of leakage current is achieved, so that an improvement in the refresh characteristics of the transistor is achieved.Type: GrantFiled: January 18, 2005Date of Patent: July 17, 2007Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Publication number: 20050263819Abstract: A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain junctions having asymmetrical junction structures, respectively, wherein the gate has a lower portion arranged on the active region of the substrate, the lower gate portion having a stepped profile having a lower surface, an upper surface and a vertically-extending side surface. The invention also provides a method for manufacturing this transistor. In accordance with this transistor structure, an increase in the dopant concentration of a storage node is prevented. Accordingly, a reduction in the amount of leakage current is achieved, so that an improvement in the refresh characteristics of the transistor is achieved.Type: ApplicationFiled: January 18, 2005Publication date: December 1, 2005Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Moon Sik Suh
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Patent number: 6930019Abstract: Disclosed is a MOS transistor formation method including the steps of: forming a gate oxide film and a gate electrode on a device region of a silicon substrate; forming a nitride film spacer on one side surface of the gate electrode; forming an interlayer dielectric layer on an upper surface of overall structure inclusive of the nitride film spacer; forming a landing plug contact hole by over-etching the interlayer dielectric layer and an active region of the silicon substrate; forming an oxide film on an upper surface of overall structure inclusive of the landing plug contact hole; forming a side wall oxide film spacer by selectively eliminating the oxide film so that the oxide film remains only on a side wall of the landing plug contact hole; forming a first landing plug pattern in a lower portion of the landing plug contact hole; eliminating exposed side wall oxide film spacer and etching inside of a first landing plug pattern, thereby forming an auxiliary groove which expands area of the landing plug contType: GrantFiled: June 24, 2004Date of Patent: August 16, 2005Assignee: Hynix Semiconductor Inc.Inventor: Moon Sik Suh
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Publication number: 20050130388Abstract: Disclosed is a MOS transistor formation method including the steps of: forming a gate oxide film and a gate electrode on a device region of a silicon substrate; forming a nitride film spacer on one side surface of the gate electrode; forming an interlayer dielectric layer on an upper surface of overall structure inclusive of the nitride film spacer; forming a landing plug contact hole by over-etching the interlayer dielectric layer and an active region of the silicon substrate; forming an oxide film on an upper surface of overall structure inclusive of the landing plug contact hole; forming a side wall oxide film spacer by selectively eliminating the oxide film so that the oxide film remains only on a side wall of the landing plug contact hole; forming a first landing plug pattern in a lower portion of the landing plug contact hole; eliminating exposed side wall oxide film spacer and etching inside of a first landing plug pattern, thereby forming an auxiliary groove which expands area of the landing plug contType: ApplicationFiled: June 24, 2004Publication date: June 16, 2005Inventor: Moon Sik Suh
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Patent number: 6762104Abstract: Disclosed is a method for fabricating a semiconductor device wherein boron-halo ion implantation is performed only to a bit-line contact part while masking a storage node contact part. The method comprises the steps of: performing a first ion implantation into the semiconductor substrate to control the threshold voltage Vt; forming a gate electrode on the semiconductor substrate in which the first ion implantation has been performed; performing a second ion implantation with a tilt of desired degree, using the gate electrode as a mask in order to control the threshold voltage; and performing a third ion implantation to form an LDD region in the substrate region at both sides of the gate electrode. In this method, the first ion implantation is performed at a range of below 90% of the whole doping concentration required to control the threshold voltage, and the second ion implantation is performed with a degree of below 30° and in two directions or four directions vertical to the gate electrode.Type: GrantFiled: December 23, 2002Date of Patent: July 13, 2004Assignee: Hynix Semiconductor Inc.Inventors: Moon Sik Suh, Sung Kye Park
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Publication number: 20030124822Abstract: Disclosed is a method for fabricating a semiconductor device wherein boron-halo ion implantation is performed only to a bit-line contact part while masking a storage node contact part. The method comprises the steps of: performing a first ion implantation into the semiconductor substrate to control the threshold voltage Vt; forming a gate electrode on the semiconductor substrate in which the first ion implantation has been performed; performing a second ion implantation with a tilt of desired degree, using the gate electrode as a mask in order to control the threshold voltage; and performing a third ion implantation to form an LDD region in the substrate region at both sides of the gate electrode. In this method, the first ion implantation is performed at a range of below 90% of the whole doping concentration required to control the threshold voltage, and the second ion implantation is performed with a degree of below 30° and in two directions or four directions vertical to the gate electrode.Type: ApplicationFiled: December 23, 2002Publication date: July 3, 2003Inventors: Moon Sik Suh, Sung Kye Park