Abstract: An elliptically polarizing plate and an organic light-emitting device. The elliptically polarizing plate has superior visibility based on excellent reflection characteristics and color characteristics on the side as well as the front, and an organic light-emitting device including the same.

Abstract: Disclosed is a method of controlling an electronic device, which includes, identifying first aggressors when at least one target victim of a plurality of logic elements in a design of an electric circuit and a plurality of aggressors are determined, the identified first aggressors having a switching time corresponding to the at least one target victim from among the plurality of aggressors, determining a number of simultaneously switching aggressors among the first aggressors by a statistical method based on a switching probability of each of the first aggressors, and calculating dynamic voltage drops caused to the at least one target victim by second aggressors of the determined number of simultaneously switching aggressors, respectively.

Abstract: Provided is a method of preparing a graft polymer, which includes: polymerizing a monomer mixture comprising a carboxylic acid monomer and methyl acrylate, wherein the carboxylic acid monomer is included at 1.5 to 2.5 wt %, and thus preparing an acrylic coagulant having an average particle diameter of 60 to 70 nm; polymerizing diene-based monomers in the presence of an emulsifier containing a salt of a compound and thus preparing a first diene-based rubber polymer; enlarging the first diene-based rubber polymer using the acrylic coagulant and thus preparing a second diene-based rubber polymer; and graft-polymerizing an aromatic vinyl-based monomer and a vinyl cyanide-based monomer to the second diene-based rubber polymer and thus preparing a graft polymer.

Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

Abstract: A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

Abstract: A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.

Abstract: A motor driven power steering apparatus includes a steering logic unit for generating a current command to operate a drive motor according to a driving condition of a vehicle, a motor speed sensor for sensing a rotation condition of the drive motor to output a motor speed, a motor control unit for receiving the current command and the motor speed from the steering logic unit and the motor speed sensor, respectively, and calculating an output voltage from a voltage table according to current-speed based on the current command and the motor speed to output a voltage command to operate the drive motor, a coordinate conversion unit for converting the two-phase voltage command outputted from the motor control unit into a three-phase voltage, and a motor driving unit for outputting the three-phase voltage converted from the coordinate conversion unit to the drive motor as a PWM voltage.

Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The method includes generating wire data corresponding to a net included in an integrated circuit, the wire data including metal layer information of a wire corresponding to the net and physical information of the wire, performing timing analysis using the physical information of the wire included in the wire data to generate timing analysis data, and changing a layout of the integrated circuit according to the timing analysis data.

Abstract: A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.

Abstract: An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.

Abstract: An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.

Abstract: A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.

Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.

Abstract: A motor driven power steering apparatus includes a steering logic unit for generating a current command to operate a drive motor according to a driving condition of a vehicle, a motor speed sensor for sensing a rotation condition of the drive motor to output a motor speed, a motor control unit for receiving the current command and the motor speed from the steering logic unit and the motor speed sensor, respectively, and calculating an output voltage from a voltage table according to current-speed based on the current command and the motor speed to output a voltage command to operate the drive motor, a coordinate conversion unit for converting the two-phase voltage command outputted from the motor control unit into a three-phase voltage, and a motor driving unit for outputting the three-phase voltage converted from the coordinate conversion unit to the drive motor as a PWM voltage.

Abstract: A control apparatus of an MDPS system may include: a current supply unit configured to drive a motor by injecting a preset frequency and magnitude of current to the motor; a torque sensor configured to sense a torque of a steering shaft; a hall sensor fault determination unit configured to determine whether a fault has occurred in a hall sensor; a torque signal processing unit configured to process a signal outputted from the torque sensor and calculate the magnitude of a torque signal; an encoder fault determination unit configured to determine whether a fault has occurred in an encoder, using the torque signal outputted from the torque signal processing unit; and a motor control unit configured to acquire a position of a motor rotor according to the determination results of the hall sensor fault determination unit and the encoder fault determination unit, and control the operation of the motor.

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

Abstract: Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing analysis for the integrated circuit. The critical paths are grouped into criticality sigma level groups according to criticality sigma levels of the critical paths, and the yield of the integrated circuit is determined based on numbers of the critical paths belonging to the respective criticality sigma level groups.