Patents by Inventor Moon Su Kim
Moon Su Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937487Abstract: An elliptically polarizing plate and an organic light-emitting device. The elliptically polarizing plate has superior visibility and excellent reflection characteristics and color characteristics on the side as well as the front, and an organic light-emitting device comprising the same.Type: GrantFiled: April 17, 2019Date of Patent: March 19, 2024Assignee: LG CHEM, LTD.Inventors: Sun Kug Kim, Hyuk Yoon, Seongho Ryu, Moon Su Park
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Publication number: 20240080011Abstract: A bulk-acoustic wave (BAW) resonator includes a central portion in which a first electrode, a piezoelectric layer, and a second electrode are sequentially stacked on a substrate, and an extension portion extending externally from the central portion, and an insertion layer and a loss prevention film are disposed in the extension portion between the substrate and the second electrode. The loss prevention film is formed to have a thickness of 50 ? to 500 ?. The insertion layer is stacked on the loss prevention film, and has a side surface opposing the central portion, the side surface is formed as a first inclined surface having a first inclination angle. The loss prevention film has a side surface opposing the central portion, the side surface is formed as a second inclined surface having a second inclination angle. The second inclination angle is formed to be greater than the first inclination angle.Type: ApplicationFiled: February 22, 2023Publication date: March 7, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Moon Chul LEE, Jae Hyoung GIL, Kwang Su KIM, Sung Jun LEE, Yong Suk KIM, Dong Hyun PARK, Tae Kyung LEE
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Patent number: 11925043Abstract: A quantum dot light-emitting device including first electrode and a second electrode, a quantum dot layer between the first electrode and the second electrode, a first electron transport layer and a second electron layer disposed between the quantum dot layer and the second electrode. The second electron transport layer is disposed between the quantum dot layer and the first electron transport layer, wherein each of the first electron transport layer and the second electron transport layer includes an inorganic material. A lowest unoccupied molecular orbital energy level of the second electron transport layer is shallower than a lowest unoccupied molecular orbital energy level of the first electron transport layer, and a lowest unoccupied molecular orbital energy level of the quantum dot layer is shallower than a lowest unoccupied molecular orbital energy level of the second electron transport layer. An electronic device including the quantum dot light-emitting device.Type: GrantFiled: October 16, 2020Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon Gyu Han, Heejae Lee, Eun Joo Jang, Tae Ho Kim, Kun Su Park, Won Sik Yoon, Hyo Sook Jang
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Patent number: 11861281Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.Type: GrantFiled: October 17, 2022Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Lee, Bong-il Park, Moon-su Kim, Sun-ik Heo
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Publication number: 20230037826Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.Type: ApplicationFiled: October 17, 2022Publication date: February 9, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Lee, Bong-il Park, Moon-su Kim, Sun-ik Heo
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Patent number: 11475195Abstract: A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.Type: GrantFiled: January 25, 2021Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Lee, Bong-il Park, Moon-su Kim, Sun-ik Heo
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Patent number: 11256846Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.Type: GrantFiled: May 7, 2019Date of Patent: February 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Su Kim, Naya Ha, Jong-Ku Kang, Andrew Paul Hoover
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Publication number: 20210173991Abstract: A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.Type: ApplicationFiled: January 25, 2021Publication date: June 10, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Lee, Bong-il Park, Moon-su Kim, Sun-ik Heo
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Patent number: 10924046Abstract: A motor driven power steering apparatus includes a steering logic unit for generating a current command to operate a drive motor according to a driving condition of a vehicle, a motor speed sensor for sensing a rotation condition of the drive motor to output a motor speed, a motor control unit for receiving the current command and the motor speed from the steering logic unit and the motor speed sensor, respectively, and calculating an output voltage from a voltage table according to current-speed based on the current command and the motor speed to output a voltage command to operate the drive motor, a coordinate conversion unit for converting the two-phase voltage command outputted from the motor control unit into a three-phase voltage, and a motor driving unit for outputting the three-phase voltage converted from the coordinate conversion unit to the drive motor as a PWM voltage.Type: GrantFiled: March 25, 2019Date of Patent: February 16, 2021Assignee: Hyundai Mobis Co., Ltd.Inventors: Moon Su Kim, Ji Hoon Yoo
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Patent number: 10902168Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The method includes generating wire data corresponding to a net included in an integrated circuit, the wire data including metal layer information of a wire corresponding to the net and physical information of the wire, performing timing analysis using the physical information of the wire included in the wire data to generate timing analysis data, and changing a layout of the integrated circuit according to the timing analysis data.Type: GrantFiled: January 4, 2018Date of Patent: January 26, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Lee, Bong-il Park, Moon-su Kim, Sun-ik Heo
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Patent number: 10796050Abstract: A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.Type: GrantFiled: May 20, 2019Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Moon Su Kim
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Patent number: 10740522Abstract: An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.Type: GrantFiled: August 21, 2019Date of Patent: August 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Moon Su Kim
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Publication number: 20200242206Abstract: An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.Type: ApplicationFiled: August 21, 2019Publication date: July 30, 2020Inventor: MOON SU KIM
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Publication number: 20200151294Abstract: A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.Type: ApplicationFiled: May 20, 2019Publication date: May 14, 2020Inventor: Moon Su KIM
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Patent number: 10546093Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.Type: GrantFiled: January 10, 2018Date of Patent: January 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Moon-Su Kim
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Publication number: 20190305706Abstract: A motor driven power steering apparatus includes a steering logic unit for generating a current command to operate a drive motor according to a driving condition of a vehicle, a motor speed sensor for sensing a rotation condition of the drive motor to output a motor speed, a motor control unit for receiving the current command and the motor speed from the steering logic unit and the motor speed sensor, respectively, and calculating an output voltage from a voltage table according to current-speed based on the current command and the motor speed to output a voltage command to operate the drive motor, a coordinate conversion unit for converting the two-phase voltage command outputted from the motor control unit into a three-phase voltage, and a motor driving unit for outputting the three-phase voltage converted from the coordinate conversion unit to the drive motor as a PWM voltage.Type: ApplicationFiled: March 25, 2019Publication date: October 3, 2019Inventors: Moon Su KIM, Ji Hoon YOO
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Patent number: 10414431Abstract: A control apparatus of an MDPS system may include: a current supply unit configured to drive a motor by injecting a preset frequency and magnitude of current to the motor; a torque sensor configured to sense a torque of a steering shaft; a hall sensor fault determination unit configured to determine whether a fault has occurred in a hall sensor; a torque signal processing unit configured to process a signal outputted from the torque sensor and calculate the magnitude of a torque signal; an encoder fault determination unit configured to determine whether a fault has occurred in an encoder, using the torque signal outputted from the torque signal processing unit; and a motor control unit configured to acquire a position of a motor rotor according to the determination results of the hall sensor fault determination unit and the encoder fault determination unit, and control the operation of the motor.Type: GrantFiled: August 25, 2017Date of Patent: September 17, 2019Assignee: HYUNDAI MOBIS CO., LTD.Inventors: Moon Su Kim, Ji Hoon Yoo
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Publication number: 20190258775Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: MOON-SU KIM, Naya Ha, Jong-ku Kang, Andrew Paul Hoover
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Patent number: 10372869Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.Type: GrantFiled: March 25, 2016Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Su Kim, Naya Ha, Jong-Ku Kang, Andrew Paul Hoover
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Patent number: 10192015Abstract: Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing analysis for the integrated circuit. The critical paths are grouped into criticality sigma level groups according to criticality sigma levels of the critical paths, and the yield of the integrated circuit is determined based on numbers of the critical paths belonging to the respective criticality sigma level groups.Type: GrantFiled: April 12, 2016Date of Patent: January 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Su Kim, Kyoung-Hwan Lim, Cheol-Jun Bae