Patents by Inventor Moon-Han Park
Moon-Han Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11069820Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: GrantFiled: April 14, 2020Date of Patent: July 20, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ho Jo, Dae Joung Kim, Jae Mun Kim, Moon Han Park, Tae Ho Cha, Jae Jong Han
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Patent number: 10755932Abstract: To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.Type: GrantFiled: July 17, 2018Date of Patent: August 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-woo Kang, Ji-ho Yoo, Dong-hoon Khang, Seon-bae Kim, Moon-han Park
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Publication number: 20200243398Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Gun Ho JO, Dae Joung KIM, Jae Mun KIM, Moon Han PARK, Tae Ho CHA, Jae Jong HAN
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Patent number: 10658249Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: GrantFiled: October 25, 2018Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ho Jo, Dae Joung Kim, Jae Mun Kim, Moon Han Park, Tae Ho Cha, Jae Jong Han
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Publication number: 20190148521Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: ApplicationFiled: October 25, 2018Publication date: May 16, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Gun Ho JO, Dae Joung KIM, Jae Mun KIM, Moon Han PARK, Tae Ho CHA, Jae Jong HAN
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Publication number: 20190139771Abstract: To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.Type: ApplicationFiled: July 17, 2018Publication date: May 9, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-woo Kang, Ji-ho Yoo, Dong-hoon Khang, Seon-bae Kim, Moon-han Park
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Patent number: 10224204Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.Type: GrantFiled: February 8, 2018Date of Patent: March 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hoon Khang, Dong-Woo Kang, Moon-Han Park, Ji-Ho Yoo, Chong-Kwang Chang
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Publication number: 20190051526Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.Type: ApplicationFiled: February 8, 2018Publication date: February 14, 2019Inventors: DONG-HOON KHANG, DONG-WOO KANG, MOON-HAN PARK, JI-HO YOO, CHONG-KWANG CHANG
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Patent number: 9793399Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.Type: GrantFiled: December 17, 2014Date of Patent: October 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Pan-Kwi Park, Koung-Min Ryu, Moon-Han Park, Hyung-suk Jung, Jong-hoon Baek, Su-Young Choi
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Publication number: 20160020324Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.Type: ApplicationFiled: December 17, 2014Publication date: January 21, 2016Inventors: Pan-Kwi Park, Koung-Min Ryu, Moon-Han Park, Hyung-suk Jung, Jong-hoon Baek, Su-Young Choi
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Patent number: 8877579Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.Type: GrantFiled: March 12, 2012Date of Patent: November 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Moon-kyun Song, Ha-jin Lim, Moon-han Park, Jin-ho Do
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Patent number: 8815673Abstract: In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.Type: GrantFiled: May 25, 2012Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-ho Do, Moon-han Park, Weon-hong Kim, Kyung-il Hong
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Patent number: 8664111Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.Type: GrantFiled: September 30, 2011Date of Patent: March 4, 2014Assignee: Samsung Electronic Co., Ltd.Inventors: Ha-Jin Lim, Moon-Han Park, Eun-Gon Kim, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
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Patent number: 8455345Abstract: A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.Type: GrantFiled: September 8, 2011Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-Jin Lim, Moon-Han Park, Min-Woo Song, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
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Publication number: 20120309145Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.Type: ApplicationFiled: March 12, 2012Publication date: December 6, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-kyun Song, Ha-jin Lim, Moon-han Park, Jin-ho Do
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Publication number: 20120309144Abstract: In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.Type: ApplicationFiled: May 25, 2012Publication date: December 6, 2012Inventors: Jin-ho Do, Moon-han Park, Weon-hong Kim, Kyung-il Hong
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Publication number: 20120083111Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.Type: ApplicationFiled: September 30, 2011Publication date: April 5, 2012Inventors: Ha-Jin Lim, Moon-Han Park, Eun-Gon Kim, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
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Publication number: 20120070975Abstract: A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.Type: ApplicationFiled: September 8, 2011Publication date: March 22, 2012Inventors: Ha-Jin Lim, Moon-Han Park, Min-Woo Song, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
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Publication number: 20100233864Abstract: Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.Type: ApplicationFiled: February 17, 2010Publication date: September 16, 2010Inventors: Ho Lee, Moon-han Park, Hwa-sung Rhee, Myung-sun Kim, Hoi-sung Chung
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Patent number: 7723193Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.Type: GrantFiled: April 30, 2008Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hwa-Sung Rhee, Hyun-Suk Kim, Ueno Tetsuji, Jae-Yoon Yoo, Seung-Hwan Lee, Ho Lee, Moon-han Park