Patents by Inventor Moonhee Oh

Moonhee Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor die for determining load of through silicon via and semiconductor device including the same
    Patent number: 11239210
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeungHan Woo, Je Min Ryu, Reum Oh, Moonhee Oh, BumSuk Lee
  • SEMICONDUCTOR DIE FOR DETERMINING LOAD OF THROUGH SILICON VIA AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20210104498
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SeungHan WOO, Je Min RYU, Reum OH, Moonhee OH, BumSuk LEE
  • Semiconductor die for determining load of through silicon via and semiconductor device including the same
    Patent number: 10916525
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeungHan Woo, Je Min Ryu, Reum Oh, Moonhee Oh, BumSuk Lee
  • Memory device comprising status circuit and operating method thereof
    Patent number: 10671464
    Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moonhee Oh, Je Min Ryu, Reum Oh, Jaeyoun Youn
  • SEMICONDUCTOR DIE FOR DETERMINING LOAD OF THROUGH SILICON VIA AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20190279963
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 12, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SeungHan WOO, Je Min Ryu, Reum Oh, Moonhee Oh, BumSuk Lee
  • MEMORY DEVICE COMPRISING STATUS CIRCUIT AND OPERATING METHOD THEREOF
    Publication number: 20180189127
    Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.
    Type: Application
    Filed: December 21, 2017
    Publication date: July 5, 2018
    Inventors: Moonhee Oh, Je Min Ryu, Reum Oh, Jaeyoun Youn