Patents by Inventor Moonhui LEE

Moonhui LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and layout method of the same
    Patent number: 12255140
    Abstract: A semiconductor device, includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and a plurality of interconnection patterns connected to the plurality of semiconductor elements, wherein the plurality of interconnection patterns include a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction, a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and a routing interconnection adjacent to at least one of the plurality of semiconductor elements in the second direction, wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second directio
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: March 18, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungil Chai, Kyunghee Shin, Daehee Lee, Moonhui Lee
  • SEMICONDUCTOR DEVICE AND LAYOUT METHOD OF THE SAME
    Publication number: 20230132080
    Abstract: A semiconductor device, includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and a plurality of interconnection patterns connected to the plurality of semiconductor elements, wherein the plurality of interconnection patterns include a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction, a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and a routing interconnection adjacent to at least one of the plurality of semiconductor elements in the second direction, wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second directio
    Type: Application
    Filed: July 18, 2022
    Publication date: April 27, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungil CHAI, Kyunghee SHIN, Daehee LEE, Moonhui LEE