Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

Abstract: A memory device includes a row decoder that receives one or more normal addresses and one or more control addresses, and a memory cell array connected to the row decoder via a plurality of word lines. In a normal operation, in response to receiving the one or more normal addresses, any one word line among the plurality of word lines is enabled. In an initialization operation, in response to receiving the one or more normal addresses and the one or more control addresses, at least two word lines among the plurality of word lines are enabled. Data of memory cells of the memory cell array connected to the enabled at least two word lines is initialized.

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.