Patents by Inventor Moonkyun Song
Moonkyun Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10217640Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.Type: GrantFiled: October 30, 2017Date of Patent: February 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Soojung Choi, Moonkyun Song, Yoon Tae Hwang, Kyumin Lee, Sangjin Hyun
-
Publication number: 20180151376Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.Type: ApplicationFiled: October 30, 2017Publication date: May 31, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Soojung Choi, Moonkyun Song, Yoon Tae Hwang, Kyumin Lee, Sangjin Hyun
-
Patent number: 9755026Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.Type: GrantFiled: April 19, 2016Date of Patent: September 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Su Yoo, WeonHong Kim, Moonkyun Song, Minjoo Lee, Soojung Choi
-
Publication number: 20170062572Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.Type: ApplicationFiled: April 19, 2016Publication date: March 2, 2017Inventors: Dong Su Yoo, WeonHong KIM, Moonkyun SONG, Minjoo LEE, Soojung CHOI
-
Patent number: 9525042Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.Type: GrantFiled: April 30, 2015Date of Patent: December 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seokjun Won, Youngmook Oh, Moonkyun Song, MinWoo Song, Namgyu Cho
-
Publication number: 20150311310Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.Type: ApplicationFiled: April 30, 2015Publication date: October 29, 2015Inventors: SEOKJUN WON, Youngmook Oh, Moonkyun Song, MinWoo Song, Namgyu Cho
-
Patent number: 9142461Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.Type: GrantFiled: May 28, 2014Date of Patent: September 22, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
-
Patent number: 9064723Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.Type: GrantFiled: January 28, 2013Date of Patent: June 23, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Seokjun Won, Youngmook Oh, Moonkyun Song, MinWoo Song, Namgyu Cho
-
Patent number: 8912611Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.Type: GrantFiled: February 26, 2014Date of Patent: December 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: WeonHong Kim, Dae-Kwon Joo, Hajin Lim, Jinho Do, Kyungil Hong, Moonkyun Song
-
Publication number: 20140273382Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinho DO, Hajin LIM, WeonHong KIM, Kyungil HONG, Moonkyun SONG
-
Patent number: 8778753Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.Type: GrantFiled: March 19, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
-
Publication number: 20140175569Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: WeonHong KIM, Dae-Kwon JOO, Hajin LIM, Jinho DO, Kyungil HONG, Moonkyun SONG
-
Patent number: 8735951Abstract: A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.Type: GrantFiled: December 16, 2011Date of Patent: May 27, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hajin Lim, Moonhan Park, Jinho Do, Moonkyun Song
-
Patent number: 8673711Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.Type: GrantFiled: September 22, 2011Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: WeonHong Kim, Dae-Kwon Joo, Hajin Lim, Jinho Do, Kyungil Hong, Moonkyun Song
-
Publication number: 20130299916Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.Type: ApplicationFiled: January 28, 2013Publication date: November 14, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seokjun Won, Youngmook Oh, Moonkyun Song, MinWoo Song, Namgyu Cho
-
Patent number: 8575705Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.Type: GrantFiled: December 9, 2010Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hajin Lim, Myungsun Kim, Hoi Sung Chung, Jinho Do, Weonhong Kim, Moonkyun Song, Dae-Kwon Joo
-
Publication number: 20120244670Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.Type: ApplicationFiled: March 19, 2012Publication date: September 27, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
-
Publication number: 20120161211Abstract: A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.Type: ApplicationFiled: December 16, 2011Publication date: June 28, 2012Inventors: Hajin LIM, Moonhan Park, Jinho Do, Moonkyun Song
-
Publication number: 20120129310Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.Type: ApplicationFiled: September 22, 2011Publication date: May 24, 2012Inventors: WeonHong KIM, Dae-Kwon Joo, Hajin Lim, Jinho Do, Kyungil Hong, Moonkyun Song
-
Publication number: 20110175141Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.Type: ApplicationFiled: December 9, 2010Publication date: July 21, 2011Inventors: Hajin LIM, Myungsun Kim, Hoi Sung Chung, Jinho Do, Weonhong Kim, Moonkyun Song, Dae-Kwon Joo