Abstract: A strain sensor may have a conductive elastic yarn including a first fiber having a predetermined length and a shape of a fiber yarn and a second fiber having electrical conductivity and a sheet shape. The strain sensor may have a pair of wiring members electrically connected to both ends of the conductive elastic yarn. The conductive elastic yarn, with the second fiber wrapped around the first fiber, is twisted in a coil shape.

Abstract: Disclosed herein are a method for generating Gaussian error data using flash memory and an apparatus using the method. The method includes receiving a request to generate Gaussian error data and delivering an operation command to flash memory; generating Gaussian error noise based on a threshold voltage that is generated when the flash memory performs the operation command; and generating Gaussian error data so as to correspond to the Gaussian error noise and providing the same.

Abstract: Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.

Abstract: Disclosed herein are a method for generating Gaussian error data using flash memory and an apparatus using the method. The method includes receiving a request to generate Gaussian error data and delivering an operation command to flash memory; generating Gaussian error noise based on a threshold voltage that is generated when the flash memory performs the operation command; and generating Gaussian error data so as to correspond to the Gaussian error noise and providing the same.

Abstract: Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.

Abstract: The present invention relates to a high-speed imaging system for measuring a target object within a sample, comprising: a light source emitting a plane wave; an angle-adjustment mirror adjusting an angle of the plane wave emitted from the light source; an optical interferometer dividing the plane wave whose angle was adjusted by the angle-adjustment mirror into a reference wave and a sample wave and forming an interference wave between the reference wave reflected from a reference mirror and the sample wave reflected from the target object; a camera module obtaining the interference wave, and an imaging controller controlling the angle-adjustment mirror to adjust the angle of the plane wave sequentially, forming a time-gated reflection matrix by using the interference waves obtained by the camera module in accordance with each angle of the plane wave, and imaging the target object based on the time-gated reflection matrix.

Abstract: The present disclosure relates to an Elizabethan collar for a pet. According to the present disclosure, since it is possible to adjust the direction of the Elizabethan collar, it is possible to increase usability of the Elizabethan collar and to enable a pet to comfortably wear the Elizabethan collar while preventing the pet from easily taking off the Elizabethan collar.

Abstract: The present invention relates to a high-speed imaging system for measuring a target object within a sample, comprising: a light source emitting a plane wave; an angle-adjustment mirror adjusting an angle of the plane wave emitted from the light source; an optical interferometer dividing the plane wave whose angle was adjusted by the angle-adjustment mirror into a reference wave and a sample wave and forming an interference wave between the reference wave reflected from a reference mirror and the sample wave reflected from the target object; a camera module obtaining the interference wave, and an imaging controller controlling the angle-adjustment mirror to adjust the angle of the plane wave sequentially, forming a time-gated reflection matrix by using the interference waves obtained by the camera module in accordance with each angle of the plane wave, and imaging the target object based on the time-gated reflection matrix.

Abstract: A PERL solar cell and a method for preparing same. In forming a back contact electrode of the PERL solar cell comprising a BSF metal layer and a bus bar electrode, the PERL solar cell has the BSF metal layer provided on opening portions of a passivation layer and has a bus bar electrode formed on the passivation layer, thereby resolving all mechanical defects generated when forming the opening portions of the passivation layer, and enhancing the strength of the solar cell. The PERL solar cell of the present disclosure comprises: a solar cell substrate; a passivation layer provided on one side of the substrate and having a plurality of opening portions which expose the surface of the substrate; a bus bar electrode provided on the passivation layer and on an area not overlapping the area on which the opening portions are provided; and a BSF metal layer provided on the passivation layer so as to fill all the plurality of opening portions.

Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

Abstract: An apparatus and method that prevent a bit error in a static random access memory (SRAM)-based Physically Unclonable function (PUF). The method for preventing an error in a PUF includes selecting any value, from a physically unclonable function based on a volatile memory device, as an input value, and checking a response corresponding to the selected input value, classifying cells having a plurality of bits corresponding to the response depending on frequency of error occurrence, calculating a number of white cells, in which an error does not occur, from classified results, and determining whether the number of white cells is greater than a preset threshold number of white cells, and selecting an input value of the physically unclonable function based on results of determination.

Abstract: A method and apparatus for controlling the operation of flash memory are provided. The apparatus for controlling the operation of flash memory includes a control unit and a voltage adjustment unit. The control unit outputs a control signal adapted to change one or more of the program, erase and read voltage conditions for the flash memory to the voltage adjustment unit in response to the input of a PUF mode selection signal. The voltage adjustment unit changes the one or more of the program, erase and read voltage conditions for the flash memory in response to the input of the control signal.

Abstract: An apparatus and method that prevent a bit error in a static random access memory (SRAM)-based Physically Unclonable function (PUF). The method for preventing an error in a PUF includes selecting any value, from a physically unclonable function based on a volatile memory device, as an input value, and checking a response corresponding to the selected input value, classifying cells having a plurality of bits corresponding to the response depending on frequency of error occurrence, calculating a number of white cells, in which an error does not occur, from classified results, and determining whether the number of white cells is greater than a preset threshold number of white cells, and selecting an input value of the physically unclonable function based on results of determination.

Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

Abstract: A method and apparatus for controlling the operation of flash memory are provided. The apparatus for controlling the operation of flash memory includes a control unit and a voltage adjustment unit. The control unit outputs a control signal adapted to change one or more of the program, erase and read voltage conditions for the flash memory to the voltage adjustment unit in response to the input of a PUF mode selection signal. The voltage adjustment unit changes the one or more of the program, erase and read voltage conditions for the flash memory in response to the input of the control signal.

Abstract: A test facility may be used to test semiconductor devices. The test facility may include a stacker part configured to communicate with a server, wherein the server includes test programs for testing semiconductor devices, and a plurality of test board parts disposed in the stacker part, at least one of the test board parts including semiconductor devices disposed thereon and configured to provide at least one of the test programs from the server to the semiconductor devices. The stacker part may include unit stackers which include shelves configured to hold the plurality of test board parts and a stacker controller configured to communicate with the test board parts in the unit stackers and the server.

Abstract: According to example embodiments, a flip chip bonding apparatus includes a metal chamber, a stage in the metal chamber, and a planar antenna in the chamber. The stage may be configured to receive a circuit board having flip chips arranged thereon. The antenna may be configured to bond the flip chips to the circuit board by inductively heating the flip chips on the circuit board.