Patents by Inventor Moo-sung Chae
Moo-sung Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545968Abstract: Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.Type: GrantFiled: May 18, 2020Date of Patent: January 3, 2023Assignee: Cadence Design Systems, Inc.Inventors: Moo Sung Chae, Thomas Evan Wilson
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Patent number: 10796746Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.Type: GrantFiled: September 21, 2018Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
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Patent number: 10545895Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.Type: GrantFiled: January 22, 2018Date of Patent: January 28, 2020Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Aaron Willey, Hari Anand Ravi, H. Md. Shuaeb Fazeel, Thomas Evan Wilson, Moo Sung Chae
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Patent number: 10387341Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.Type: GrantFiled: November 16, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
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Publication number: 20190087366Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
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Publication number: 20190027208Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.Type: ApplicationFiled: September 21, 2018Publication date: January 24, 2019Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
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Patent number: 10180920Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.Type: GrantFiled: April 26, 2018Date of Patent: January 15, 2019Assignee: Micron Technology, Inc.Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
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Patent number: 10128965Abstract: A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage. The device includes an output inverter coupled in series with the input inverter to provide an output signal having a parity of the input signal. A system including the above device, and a method for calibrating the above device, are also provided.Type: GrantFiled: September 1, 2017Date of Patent: November 13, 2018Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Thomas E. Wilson, Moo Sung Chae
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Patent number: 10115449Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.Type: GrantFiled: January 25, 2017Date of Patent: October 30, 2018Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
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Publication number: 20180246822Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.Type: ApplicationFiled: April 26, 2018Publication date: August 30, 2018Applicant: Micron Technology, Inc.Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
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Patent number: 9965408Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.Type: GrantFiled: May 14, 2015Date of Patent: May 8, 2018Assignee: Micron Technology, Inc.Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
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Publication number: 20170133080Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: DEAN GANS, MOO SUNG CHAE, DANIEL SKINNER
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Patent number: 9601182Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.Type: GrantFiled: May 8, 2015Date of Patent: March 21, 2017Assignee: Micron Technology, Inc.Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
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Publication number: 20160335204Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
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Publication number: 20160329090Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.Type: ApplicationFiled: May 8, 2015Publication date: November 10, 2016Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
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Patent number: 7539826Abstract: By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.Type: GrantFiled: April 29, 2005Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Moo-Sung Chae, Kye-Hyun Kyung
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Patent number: 7298667Abstract: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.Type: GrantFiled: August 12, 2005Date of Patent: November 20, 2007Assignee: Samsung Electronic Co., Ltd.Inventors: Reum Oh, Sang-bo Lee, Moo-sung Chae, Ho-young Song
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Patent number: 7257754Abstract: A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.Type: GrantFiled: September 29, 2004Date of Patent: August 14, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Moo-Sung Chae, Hye-In Choi
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Publication number: 20060077751Abstract: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.Type: ApplicationFiled: August 12, 2005Publication date: April 13, 2006Inventors: Reum Oh, Sang-bo Lee, Moo-sung Chae, Ho-young Song
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Patent number: 6992949Abstract: There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal.Type: GrantFiled: September 15, 2004Date of Patent: January 31, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Moo-sung Chae, Hyung-chan Choi