Abstract: A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die.

Abstract: A system employs a flexible optical media, two connectors, and a mechanism such as a magnet that brings the connector together when the connectors are close to each other. The optical media is able to guide optical signals, and one connector is attached to an end of the optical media. Each connector also has alignment features and provides paths for the optical signals. The alignment features of each connector are shaped to mate with the alignment features of the other connector and to shift the connectors relative to each other as the mechanism pushes the connector together. The alignment features further have seated positions at which the paths in one connector are aligned with the paths in the other connector and separated by a free space gap.

Abstract: An optical fiber connector is disclosed. The optical fiber connector comprises a form having a curved surface with a first end near the bottom surface of the form. The curved surface is perpendicular to the bottom surface of the form at the first end. A first plurality of active optical fibers are positioned along the curved surface of the form in a side-by side arrangement with the tips of each of the first plurality of optical fibers adjacent to the first end of the curved surface. The ends of each of the first plurality of active optical fibers have been striped down to cladding and the cladding of each optical fiber contacts the cladding of the adjacent optical fibers. An inner cover is attached to the form thereby capturing the first plurality of active optical fibers between the curved surface of the form and an inside curved surface in the inner cover.

Abstract: Various embodiments of the present invention are directed to arrangements of multiple optical buses to create scalable optical interconnect fabrics for computer systems. In one aspect, a multi-bus fabric (102) for transmitting optical signals between a plurality of nodes (108-111) comprises a plurality of optical buses (104-107). Each optical bus is optically coupled to each node of the plurality of nodes, and each optical bus is configured to so that one node broadcasts optical signals generated by the node to the other nodes of the plurality of nodes.

Abstract: Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter.

Abstract: In a method for managing a memory segment through use of a memory virtual appliance, data is encapsulated with the memory virtual appliance, in which the memory virtual appliance comprises a virtual machine configured to manage a memory segment in a physical memory. In addition, the memory virtual appliance is implemented using a virtualization wrapper comprising computer readable code enabling the encapsulated data to be shared among a plurality of clients. Moreover, the encapsulated data is stored in the memory segment controlled by the memory virtual appliance.

Abstract: Methods and systems are provided that prevent buffer overflow in multibus systems. In one aspect, a method for controlling the flow of data in a multibus system includes, for each node having an associated broadcast bus in the multibus system, generating status information regarding available data storage space of each receive buffer of the node. The method includes broadcasting the status information to the other nodes connected to the broadcast bus and collecting status information regarding the available storage space of receive buffers of the other nodes connected to the broadcast bus. The method also includes determining whether or not to send data from the node to at least one of the other nodes over the broadcast bus based on the collected status information.

Abstract: Systems and methods are provided for modulating, channels in dense wavelength division multiplexing (“DWDM”) systems. In one aspect, a modulation and wavelength division multiplexing system includes a channel source and a waveguide tree structure disposed on a substrate. The tree structure includes waveguides branching from a root waveguide. The waveguides include two or more terminus waveguides coupled to the channel source. The system also includes one or more modulator arrays disposed on the substrate. Each modulator array is optically coupled to one of the two or more terminus waveguides and is configured to modulate channels injected into a terminus waveguide from the channel source to produce corresponding optical signals that propagate from the terminus waveguide along one or more of the waveguides to the root waveguide.

Abstract: Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.

Abstract: A memory apparatus (100, 200, 300, 500, 600, 700) has a plurality of memory banks (d0 to d7, m0 to m3, p, p0, p1), wherein a write or erase operation to the memory banks (d0 to d7, m0 to m3, p, p0, p1) is substantially slower than a read operation to the banks (d0 to d7, m0 to m3, p, p0, p1). The memory apparatus (100, 200, 300, 500, 600, 700) is configured to read a redundant storage of data instead of a primary storage location in the memory banks (d0 to d7, m0 to m3, p, p0, p1) for the data or reconstruct requested data in response to a query for the data when the primary storage location is undergoing at least one of a write operation and an erase operation.

Abstract: A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.

Abstract: Various embodiments of the present invention relate to systems and methods for achieving low-latency, prioritized, distributed optical-base arbitration. In one embodiment, an optical arbitration system (100,1100) comprises a waveguide (102,1102) having a first end and a second end, and a source (104,1104) optically coupled to the first end of the waveguide and configured to input at least one wavelength of light into the waveguide. The system also includes a number of wavelength selective elements (106-109,1106-1109) optically coupled to the waveguide. Each wavelength selective element is capable of extracting a wavelength of light from the waveguide when activated by an electronically coupled node. An arbiter (110,116,120,1112,1116,1120) is optically coupled to the second end of the waveguide and to the waveguide between the source and a wavelength selective element located closest to the source along the waveguide.

Abstract: Various embodiments of the present invention relate to systems and methods for monitoring and tuning detector and modulator resonators during operation. Aspects of the present invention use DC balanced coding of data in optical signals tune and monitor the performance of a resonator. Whether the resonator is being used as a modulator or a detector, the intensity of the light coupled into the resonator is DC balanced and varies as a function of the data being transmitted. Average intensity variations of the light scattered from the resonator are converted into an electronic feedback signal, which is used to determine appropriate levels of thermal and electronic tuning applied to the resonator.

Abstract: One embodiment of the present invention is directed to a networking system comprising a sending device, a receiving device, electronic communications components and transmission media through which the sending device and receiving device exchange data packets, and a networking protocol implemented in executable routines, firmware, hardware, or a combination of two or more of executable routines, firmware, hardware that provides for transmission of data in an ordered set of data packets through a sequence established between the sending device and receiving device as a result of transmitting a first data packet from the sending device to the receiving device and returning an acknowledgement by the receiving device to the sending device.

Abstract: Embodiments of the present invention are directed to optical broadcast systems (100,140,160,180). The nodes of the system can be any combination of cores, caches, input/output devices, and memory, or any other information processing, transmitting, or storing device. The optical broadcast system includes an optical broadcast bus (142,162,182). Any node of the system in optical communication with the broadcast bus can broadcast information in optical signals to all other nodes in optical communication with the broadcast bus.

Abstract: Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.

Abstract: Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

Abstract: Embodiments of the present invention are directed to optical multiprocessing buses. In one embodiment, an optical broadcast bus includes a repeater, a fan-in bus optically coupled to a number of nodes and the repeater, and a fan-out bus optically coupled to the nodes and the repeater. The fan-in bus is configured to receive optical signals from each node and transmit the optical signals to the repeater, which regenerates the optical signals. The fan-out bus is configured to receive the regenerated optical signals output from the repeater and distribute the regenerated optical signals to the nodes. The repeater can also serve as an arbiter by granting one node at a time access to the fan-in bus.

Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted (401) from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.

Abstract: A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die.